Lines Matching full:cmu_peric0
216 cmu_peric0: clock-controller@10400000 { label
234 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_SYSREG_PERIC0_PCLK>;
240 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_UART_DBG_PCLK>,
241 <&cmu_peric0 CLK_GOUT_PERIC0_UART_DBG_EXT_UCLK>;
253 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_USI00_I_PCLK>,
254 <&cmu_peric0 CLK_GOUT_PERIC0_USI00_I_SCLK_USI>;
264 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_USI00_I_PCLK>;
275 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_USI00_I_PCLK>,
276 <&cmu_peric0 CLK_GOUT_PERIC0_USI00_I_SCLK_USI>;
289 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_USI00_I_PCLK>,
290 <&cmu_peric0 CLK_GOUT_PERIC0_USI00_I_SCLK_USI>;
303 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_USI00_I_PCLK>;
315 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_USI01_I_PCLK>,
316 <&cmu_peric0 CLK_GOUT_PERIC0_USI01_I_SCLK_USI>;
326 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_USI01_I_PCLK>;
337 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_USI01_I_PCLK>,
338 <&cmu_peric0 CLK_GOUT_PERIC0_USI01_I_SCLK_USI>;
351 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_USI01_I_PCLK>,
352 <&cmu_peric0 CLK_GOUT_PERIC0_USI01_I_SCLK_USI>;
365 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_USI01_I_PCLK>;
377 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_USI02_I_PCLK>,
378 <&cmu_peric0 CLK_GOUT_PERIC0_USI02_I_SCLK_USI>;
388 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_USI02_I_PCLK>;
399 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_USI02_I_PCLK>,
400 <&cmu_peric0 CLK_GOUT_PERIC0_USI02_I_SCLK_USI>;
413 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_USI02_I_PCLK>,
414 <&cmu_peric0 CLK_GOUT_PERIC0_USI02_I_SCLK_USI>;
427 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_USI02_I_PCLK>;
439 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_USI03_I_PCLK>,
440 <&cmu_peric0 CLK_GOUT_PERIC0_USI03_I_SCLK_USI>;
450 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_USI03_I_PCLK>;
461 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_USI03_I_PCLK>,
462 <&cmu_peric0 CLK_GOUT_PERIC0_USI03_I_SCLK_USI>;
475 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_USI03_I_PCLK>,
476 <&cmu_peric0 CLK_GOUT_PERIC0_USI03_I_SCLK_USI>;
489 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_USI03_I_PCLK>;