Lines Matching full:cmu_fsys
416 cmu_fsys: clock-controller@156e0000 {
1760 clocks = <&cmu_fsys CLK_ACLK_USBDRD30>,
1761 <&cmu_fsys CLK_SCLK_USBDRD30>,
1762 <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK>,
1763 <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK>;
1772 clocks = <&cmu_fsys CLK_SCLK_USBDRD30>,
1773 <&cmu_fsys CLK_ACLK_USBDRD30>,
1774 <&cmu_fsys CLK_SCLK_USBDRD30>;
1786 clocks = <&cmu_fsys CLK_ACLK_USBDRD30>, <&xxti>,
1787 <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK>,
1788 <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK>,
1789 <&cmu_fsys CLK_SCLK_USBDRD30>;
1800 clocks = <&cmu_fsys CLK_ACLK_USBHOST30>, <&xxti>,
1801 <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK>,
1802 <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK>,
1803 <&cmu_fsys CLK_SCLK_USBHOST30>;
1813 clocks = <&cmu_fsys CLK_ACLK_USBHOST30>,
1814 <&cmu_fsys CLK_SCLK_USBHOST30>,
1815 <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK>,
1816 <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK>;
1825 clocks = <&cmu_fsys CLK_SCLK_USBHOST30>,
1826 <&cmu_fsys CLK_ACLK_USBHOST30>,
1827 <&cmu_fsys CLK_SCLK_USBHOST30>;
1843 clocks = <&cmu_fsys CLK_ACLK_MMC0>,
1844 <&cmu_fsys CLK_SCLK_MMC0>;
1857 clocks = <&cmu_fsys CLK_ACLK_MMC1>,
1858 <&cmu_fsys CLK_SCLK_MMC1>;
1871 clocks = <&cmu_fsys CLK_ACLK_MMC2>,
1872 <&cmu_fsys CLK_SCLK_MMC2>;
1882 clocks = <&cmu_fsys CLK_PDMA0>;
1891 clocks = <&cmu_fsys CLK_PDMA1>;
1970 clocks = <&cmu_fsys CLK_PCIE>,
1971 <&cmu_fsys CLK_PCLK_PCIE_PHY>;