Lines Matching +full:0 +full:x0c011000
48 #clock-cells = <0>;
53 #size-cells = <0>;
91 reg = <0x100>;
96 i-cache-size = <0x8000>;
99 d-cache-size = <0x8000>;
109 reg = <0x101>;
112 i-cache-size = <0x8000>;
115 d-cache-size = <0x8000>;
125 reg = <0x102>;
128 i-cache-size = <0x8000>;
131 d-cache-size = <0x8000>;
141 reg = <0x103>;
144 i-cache-size = <0x8000>;
147 d-cache-size = <0x8000>;
153 cpu4: cpu@0 {
157 reg = <0x0>;
162 i-cache-size = <0xc000>;
165 d-cache-size = <0x8000>;
175 reg = <0x1>;
178 i-cache-size = <0xc000>;
181 d-cache-size = <0x8000>;
191 reg = <0x2>;
194 i-cache-size = <0xc000>;
197 d-cache-size = <0x8000>;
207 reg = <0x3>;
210 i-cache-size = <0xc000>;
213 d-cache-size = <0x8000>;
223 cache-size = <0x200000>;
232 cache-size = <0x40000>;
238 cluster_a53_opp_table: opp-table-0 {
353 cpu_off = <0x84000002>;
354 cpu_on = <0xc4000003>;
357 soc: soc@0 {
361 ranges = <0x0 0x0 0x0 0x18000000>;
366 reg = <0x10000000 0x100>;
371 reg = <0x10030000 0x1000>;
386 reg = <0x10fc0000 0x1000>;
395 reg = <0x105b0000 0x2000>;
406 reg = <0x14c80000 0x1000>;
412 reg = <0x10040000 0x1000>;
418 reg = <0x156e0000 0x1000>;
445 reg = <0x12460000 0x1000>;
459 reg = <0x13b90000 0x1000>;
485 reg = <0x114c0000 0x1000>;
494 reg = <0x13600000 0x1000>;
503 reg = <0x14800000 0x1000>;
512 reg = <0x13400000 0x1000>;
521 reg = <0x14aa0000 0x2000>;
531 reg = <0x13cf0000 0x1000>;
545 reg = <0x11900000 0x2000>;
554 reg = <0x11800000 0x2000>;
563 reg = <0x150d0000 0x1000>;
577 reg = <0x15280000 0x1000>;
587 reg = <0x14f80000 0x1000>;
597 reg = <0x146d0000 0x1000>;
611 reg = <0x120d0000 0x1000>;
627 reg = <0x145d0000 0x1000>;
649 reg = <0x11060000 0x1000>;
664 reg = <0x11140000 0x1000>;
673 reg = <0x105c4000 0x20>;
674 #power-domain-cells = <0>;
680 reg = <0x105c4020 0x20>;
681 #power-domain-cells = <0>;
688 reg = <0x105c4040 0x20>;
689 #power-domain-cells = <0>;
695 reg = <0x105c4060 0x20>;
696 #power-domain-cells = <0>;
702 reg = <0x105c4080 0x20>;
703 #power-domain-cells = <0>;
709 reg = <0x105c40a0 0x20>;
710 #power-domain-cells = <0>;
716 reg = <0x105c40c0 0x20>;
717 #power-domain-cells = <0>;
723 reg = <0x105c4120 0x20>;
724 #power-domain-cells = <0>;
730 reg = <0x105c4140 0x20>;
731 #power-domain-cells = <0>;
738 reg = <0x105c4180 0x20>;
739 #power-domain-cells = <0>;
745 reg = <0x105c41c0 0x20>;
746 #power-domain-cells = <0>;
752 reg = <0x10060000 0x200>;
757 #thermal-sensor-cells = <0>;
763 reg = <0x10068000 0x200>;
768 #thermal-sensor-cells = <0>;
774 reg = <0x10070000 0x200>;
779 #thermal-sensor-cells = <0>;
785 reg = <0x10078000 0x200>;
790 #thermal-sensor-cells = <0>;
796 reg = <0x1007c000 0x200>;
801 #thermal-sensor-cells = <0>;
808 reg = <0x101c0000 0x800>;
827 reg = <0x10480000 0x2000>;
833 reg = <0x10490000 0x2000>;
839 reg = <0x104b0000 0x2000>;
845 reg = <0x104c0000 0x2000>;
851 reg = <0x10580000 0x1a20>, <0x11090000 0x100>;
862 reg = <0x114b0000 0x1000>;
869 reg = <0x10fe0000 0x1000>;
875 reg = <0x14ca0000 0x1000>;
881 reg = <0x14cb0000 0x1000>;
887 reg = <0x15690000 0x1000>;
893 reg = <0x11090000 0x1000>;
899 reg = <0x14cd0000 0x1000>;
905 reg = <0x14cc0000 0x1100>;
911 reg = <0x14ce0000 0x1100>;
917 reg = <0x105c0000 0x5008>;
933 offset = <0x400>; /* SWRESET */
934 mask = <0x1>;
942 reg = <0x11001000 0x1000>,
943 <0x11002000 0x2000>,
944 <0x11004000 0x2000>,
945 <0x11006000 0x2000>;
946 interrupts = <GIC_PPI 9 0xf04>;
951 reg = <0x13800000 0x2104>;
980 #size-cells = <0>;
982 port@0 {
983 reg = <0>;
994 reg = <0x13880000 0x20b8>;
1024 reg = <0x13900000 0xc0>;
1041 #size-cells = <0>;
1045 #size-cells = <0>;
1047 port@0 {
1048 reg = <0>;
1058 reg = <0x13930000 0x48>;
1068 #size-cells = <0>;
1070 port@0 {
1071 reg = <0>;
1089 reg = <0x13970000 0x70000>;
1109 #sound-dai-cells = <0>;
1114 reg = <0x13af0000 0x80>;
1120 reg = <0x13b80000 0x1010>;
1126 reg = <0x120f0000 0x1020>;
1132 reg = <0x145f0000 0x1038>;
1138 reg = <0x156f0000 0x1044>;
1143 reg = <0x13c00000 0x1000>;
1158 reg = <0x13c10000 0x1000>;
1173 reg = <0x13c20000 0x1000>;
1188 reg = <0x14ac0000 0x5000>;
1239 reg = <0x15000000 0x1294>;
1240 interrupts = <0 402 IRQ_TYPE_LEVEL_HIGH>;
1251 reg = <0x15010000 0x1294>;
1252 interrupts = <0 403 IRQ_TYPE_LEVEL_HIGH>;
1263 reg = <0x15020000 0x10000>;
1276 reg = <0x152e0000 0x10000>;
1289 reg = <0x13a00000 0x1000>;
1295 #iommu-cells = <0>;
1300 reg = <0x13a10000 0x1000>;
1305 #iommu-cells = <0>;
1311 reg = <0x13a20000 0x1000>;
1316 #iommu-cells = <0>;
1322 reg = <0x13a30000 0x1000>;
1327 #iommu-cells = <0>;
1333 reg = <0x13c80000 0x1000>;
1338 #iommu-cells = <0>;
1344 reg = <0x13c90000 0x1000>;
1349 #iommu-cells = <0>;
1355 reg = <0x13ca0000 0x1000>;
1360 #iommu-cells = <0>;
1366 reg = <0x15040000 0x1000>;
1371 #iommu-cells = <0>;
1377 reg = <0x15050000 0x1000>;
1382 #iommu-cells = <0>;
1388 reg = <0x15060000 0x1000>;
1393 #iommu-cells = <0>;
1399 reg = <0x15200000 0x1000>;
1404 #iommu-cells = <0>;
1410 reg = <0x15210000 0x1000>;
1415 #iommu-cells = <0>;
1421 reg = <0x14c10000 0x100>;
1427 pinctrl-0 = <&uart0_bus>;
1433 reg = <0x14c20000 0x100>;
1439 pinctrl-0 = <&uart1_bus>;
1445 reg = <0x14c30000 0x100>;
1451 pinctrl-0 = <&uart2_bus>;
1457 reg = <0x14d20000 0x100>;
1462 #size-cells = <0>;
1467 samsung,spi-src-clk = <0>;
1469 pinctrl-0 = <&spi0_bus>;
1476 reg = <0x14d30000 0x100>;
1481 #size-cells = <0>;
1486 samsung,spi-src-clk = <0>;
1488 pinctrl-0 = <&spi1_bus>;
1495 reg = <0x14d40000 0x100>;
1500 #size-cells = <0>;
1505 samsung,spi-src-clk = <0>;
1507 pinctrl-0 = <&spi2_bus>;
1514 reg = <0x14d50000 0x100>;
1519 #size-cells = <0>;
1524 samsung,spi-src-clk = <0>;
1526 pinctrl-0 = <&spi3_bus>;
1533 reg = <0x14d00000 0x100>;
1538 #size-cells = <0>;
1543 samsung,spi-src-clk = <0>;
1545 pinctrl-0 = <&spi4_bus>;
1552 reg = <0x14d10000 0x100>;
1562 reg = <0x14d60000 0x100>;
1577 reg = <0x14dd0000 0x100>;
1583 samsung,pwm-outputs = <0>, <1>, <2>, <3>;
1593 reg = <0x14e40000 0x1000>;
1596 #size-cells = <0>;
1598 pinctrl-0 = <&hs_i2c0_bus>;
1607 reg = <0x14e50000 0x1000>;
1610 #size-cells = <0>;
1612 pinctrl-0 = <&hs_i2c1_bus>;
1621 reg = <0x14e60000 0x1000>;
1624 #size-cells = <0>;
1626 pinctrl-0 = <&hs_i2c2_bus>;
1635 reg = <0x14e70000 0x1000>;
1638 #size-cells = <0>;
1640 pinctrl-0 = <&hs_i2c3_bus>;
1649 reg = <0x14ec0000 0x1000>;
1652 #size-cells = <0>;
1654 pinctrl-0 = <&hs_i2c4_bus>;
1663 reg = <0x14ed0000 0x1000>;
1666 #size-cells = <0>;
1668 pinctrl-0 = <&hs_i2c5_bus>;
1677 reg = <0x14ee0000 0x1000>;
1680 #size-cells = <0>;
1682 pinctrl-0 = <&hs_i2c6_bus>;
1691 reg = <0x14ef0000 0x1000>;
1694 #size-cells = <0>;
1696 pinctrl-0 = <&hs_i2c7_bus>;
1705 reg = <0x14d90000 0x1000>;
1708 #size-cells = <0>;
1710 pinctrl-0 = <&hs_i2c8_bus>;
1719 reg = <0x14da0000 0x1000>;
1722 #size-cells = <0>;
1724 pinctrl-0 = <&hs_i2c9_bus>;
1733 reg = <0x14de0000 0x1000>;
1736 #size-cells = <0>;
1738 pinctrl-0 = <&hs_i2c10_bus>;
1747 reg = <0x14df0000 0x1000>;
1750 #size-cells = <0>;
1752 pinctrl-0 = <&hs_i2c11_bus>;
1767 ranges = <0x0 0x15400000 0x10000>;
1770 usbdrd_dwc3: usb@0 {
1776 reg = <0x0 0x10000>;
1778 phys = <&usbdrd30_phy 0>, <&usbdrd30_phy 1>;
1785 reg = <0x15500000 0x100>;
1799 reg = <0x15580000 0x100>;
1820 ranges = <0x0 0x15a00000 0x10000>;
1823 usbhost_dwc3: usb@0 {
1829 reg = <0x0 0x10000>;
1831 phys = <&usbhost30_phy 0>, <&usbhost30_phy 1>;
1841 #size-cells = <0>;
1842 reg = <0x15540000 0x2000>;
1846 fifo-depth = <0x40>;
1855 #size-cells = <0>;
1856 reg = <0x15550000 0x2000>;
1860 fifo-depth = <0x40>;
1869 #size-cells = <0>;
1870 reg = <0x15560000 0x2000>;
1874 fifo-depth = <0x40>;
1880 reg = <0x15610000 0x1000>;
1889 reg = <0x15600000 0x1000>;
1898 reg = <0x11400000 0x100>, <0x11500000 0x08>;
1908 reg = <0x11420000 0x1000>;
1919 reg = <0x11440000 0x100>;
1920 dmas = <&adma 0>, <&adma 2>;
1924 #size-cells = <0>;
1931 pinctrl-0 = <&i2s0_bus>;
1939 reg = <0x11460000 0x100>;
1945 pinctrl-0 = <&uart_aud_bus>;
1953 reg = <0x15680000 0x1000>;
1956 #phy-cells = <0>;
1962 reg = <0x15700000 0x1000>, <0x156b0000 0x1000>,
1963 <0x0c000000 0x1000>;
1975 bus-range = <0x00 0xff>;
1977 ranges = <0x81000000 0 0 0x0c001000 0 0x00010000>,
1978 <0x82000000 0 0x0c011000 0x0c011000 0 0x03feefff>;