Lines Matching +full:0 +full:xc300
26 #size-cells = <0>;
28 cpu0: cpu@0 {
31 reg = <0x0>;
33 cpu-release-addr = <0x0 0xfff8>;
40 reg = <0x1>;
42 cpu-release-addr = <0x0 0xfff8>;
49 reg = <0x2>;
51 cpu-release-addr = <0x0 0xfff8>;
58 reg = <0x3>;
60 cpu-release-addr = <0x0 0xfff8>;
75 ranges = <0x00 0x00 0x81000000 0x4000>;
80 #address-cells = <0>;
82 reg = <0x1000 0x1000>,
83 <0x2000 0x2000>;
107 #clock-cells = <0>;
114 #clock-cells = <0>;
123 ranges = <0x00 0x00 0x80000000 0x281000>;
127 reg = <0x2000 0x1000>;
136 reg = <0xc200 0x100>;
148 reg = <0xc300 0x100>;
154 #size-cells = <0>;
158 #trigger-source-cells = <0>;
163 #trigger-source-cells = <0>;
169 reg = <0xc400 0x100>;
175 #size-cells = <0>;
179 #trigger-source-cells = <0>;
184 #trigger-source-cells = <0>;
190 reg = <0xd000 0x8c8>;
196 #size-cells = <0>;
200 #trigger-source-cells = <0>;
205 #trigger-source-cells = <0>;
213 ranges = <0 0x80000 0x50000>;
215 ethernet-switch@0 {
217 reg = <0x0 0x40000>,
218 <0x40000 0x110>,
219 <0x40340 0x30>,
220 <0x40380 0x30>,
221 <0x40600 0x34>,
222 <0x40800 0x208>;
231 #size-cells = <0>;
235 #size-cells = <0>;
237 port@0 {
238 reg = <0>;
276 reg = <0x405c0 0x8>;
278 #size-cells = <0>;
305 reg = <0x280000 0x1000>;
313 reg = <0x2800c0 0x40>;
323 ranges = <0x00 0x00 0xff800000 0x3000>;
327 reg = <0x400 0x4c>;
328 ranges = <0x0 0x400 0x4c>;
333 timer@0 {
335 reg = <0x0 0x28>;
340 reg = <0x28 0x8>;
347 reg = <0x500 0x28>, <0x528 0x28>;
355 reg = <0x560 0x10>;
565 reg = <0x640 0x18>;
574 reg = <0x800 0xdc>;
577 #size-cells = <0>;
582 #size-cells = <0>;
583 compatible = "brcm,bcm4908-hsspi", "brcm,bcmbca-hsspi-v1.0";
584 reg = <0x1000 0x600>;
594 #size-cells = <0>;
596 reg = <0x1800 0x600>, <0x2000 0x10>;
602 nandcs: nand@0 {
604 reg = <0>;
610 reg = <0x2100 0x58>;
613 pinctrl-0 = <&pins_i2c_a>;
619 reg = <0x2600 0xe4>;
623 ranges = <0x00 0x2600 0xe4>;
627 reg = <0x44 0x04>;
636 offset = <0x34>;