Lines Matching +full:psci +full:- +full:0
4 * Copyright (c) 2013-2014 ARM Ltd.
9 /dts-v1/;
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/arm/coresight-cti-dt.h>
13 #include "juno-base.dtsi"
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
27 stdout-path = "serial0:115200n8";
30 psci {
31 compatible = "arm,psci-0.2";
36 #address-cells = <2>;
37 #size-cells = <0>;
39 cpu-map {
65 idle-states {
66 entry-method = "psci";
68 CPU_SLEEP_0: cpu-sleep-0 {
69 compatible = "arm,idle-state";
70 arm,psci-suspend-param = <0x0010000>;
71 local-timer-stop;
72 entry-latency-us = <300>;
73 exit-latency-us = <1200>;
74 min-residency-us = <2000>;
77 CLUSTER_SLEEP_0: cluster-sleep-0 {
78 compatible = "arm,idle-state";
79 arm,psci-suspend-param = <0x1010000>;
80 local-timer-stop;
81 entry-latency-us = <400>;
82 exit-latency-us = <1200>;
83 min-residency-us = <2500>;
87 A57_0: cpu@0 {
88 compatible = "arm,cortex-a57";
89 reg = <0x0 0x0>;
91 enable-method = "psci";
92 i-cache-size = <0xc000>;
93 i-cache-line-size = <64>;
94 i-cache-sets = <256>;
95 d-cache-size = <0x8000>;
96 d-cache-line-size = <64>;
97 d-cache-sets = <256>;
98 next-level-cache = <&A57_L2>;
99 clocks = <&scpi_dvfs 0>;
100 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
101 capacity-dmips-mhz = <1024>;
102 dynamic-power-coefficient = <530>;
106 compatible = "arm,cortex-a57";
107 reg = <0x0 0x1>;
109 enable-method = "psci";
110 i-cache-size = <0xc000>;
111 i-cache-line-size = <64>;
112 i-cache-sets = <256>;
113 d-cache-size = <0x8000>;
114 d-cache-line-size = <64>;
115 d-cache-sets = <256>;
116 next-level-cache = <&A57_L2>;
117 clocks = <&scpi_dvfs 0>;
118 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
119 capacity-dmips-mhz = <1024>;
120 dynamic-power-coefficient = <530>;
124 compatible = "arm,cortex-a53";
125 reg = <0x0 0x100>;
127 enable-method = "psci";
128 i-cache-size = <0x8000>;
129 i-cache-line-size = <64>;
130 i-cache-sets = <256>;
131 d-cache-size = <0x8000>;
132 d-cache-line-size = <64>;
133 d-cache-sets = <128>;
134 next-level-cache = <&A53_L2>;
136 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
137 capacity-dmips-mhz = <578>;
138 dynamic-power-coefficient = <140>;
142 compatible = "arm,cortex-a53";
143 reg = <0x0 0x101>;
145 enable-method = "psci";
146 i-cache-size = <0x8000>;
147 i-cache-line-size = <64>;
148 i-cache-sets = <256>;
149 d-cache-size = <0x8000>;
150 d-cache-line-size = <64>;
151 d-cache-sets = <128>;
152 next-level-cache = <&A53_L2>;
154 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
155 capacity-dmips-mhz = <578>;
156 dynamic-power-coefficient = <140>;
160 compatible = "arm,cortex-a53";
161 reg = <0x0 0x102>;
163 enable-method = "psci";
164 i-cache-size = <0x8000>;
165 i-cache-line-size = <64>;
166 i-cache-sets = <256>;
167 d-cache-size = <0x8000>;
168 d-cache-line-size = <64>;
169 d-cache-sets = <128>;
170 next-level-cache = <&A53_L2>;
172 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
173 capacity-dmips-mhz = <578>;
174 dynamic-power-coefficient = <140>;
178 compatible = "arm,cortex-a53";
179 reg = <0x0 0x103>;
181 enable-method = "psci";
182 i-cache-size = <0x8000>;
183 i-cache-line-size = <64>;
184 i-cache-sets = <256>;
185 d-cache-size = <0x8000>;
186 d-cache-line-size = <64>;
187 d-cache-sets = <128>;
188 next-level-cache = <&A53_L2>;
190 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
191 capacity-dmips-mhz = <578>;
192 dynamic-power-coefficient = <140>;
195 A57_L2: l2-cache0 {
197 cache-unified;
198 cache-size = <0x200000>;
199 cache-line-size = <64>;
200 cache-sets = <2048>;
201 cache-level = <2>;
204 A53_L2: l2-cache1 {
206 cache-unified;
207 cache-size = <0x100000>;
208 cache-line-size = <64>;
209 cache-sets = <1024>;
210 cache-level = <2>;
214 pmu-a57 {
215 compatible = "arm,cortex-a57-pmu";
218 interrupt-affinity = <&A57_0>,
222 pmu-a53 {
223 compatible = "arm,cortex-a53-pmu";
228 interrupt-affinity = <&A53_0>,
260 remote-endpoint = <&replicator_in_port0>;
264 remote-endpoint = <&etf0_out_port>;
268 remote-endpoint = <&main_funnel_in_port2>;
275 remote-endpoint = <&stm_out_port>;