Lines Matching +full:ete +full:- +full:0
1 // SPDX-License-Identifier: GPL-2.0
5 * Architecture Envelope Model (AEM) ARMv8-A
11 /dts-v1/;
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 /memreserve/ 0x80000000 0x00010000;
17 #include "rtsm_ve-motherboard.dtsi"
18 #include "rtsm_ve-motherboard-rs2.dtsi"
22 compatible = "arm,fvp-base-revc", "arm,vexpress";
23 interrupt-parent = <&gic>;
24 #address-cells = <2>;
25 #size-cells = <2>;
28 stdout-path = "serial0:115200n8";
39 compatible = "arm,psci-0.2";
44 #address-cells = <2>;
45 #size-cells = <0>;
47 idle-states {
48 entry-method = "psci";
50 CPU_SLEEP_0: cpu-sleep-0 {
51 compatible = "arm,idle-state";
52 local-timer-stop;
53 arm,psci-suspend-param = <0x0010000>;
54 entry-latency-us = <40>;
55 exit-latency-us = <100>;
56 min-residency-us = <150>;
60 CLUSTER_SLEEP_0: cluster-sleep-0 {
61 compatible = "arm,idle-state";
62 local-timer-stop;
63 arm,psci-suspend-param = <0x1010000>;
64 entry-latency-us = <500>;
65 exit-latency-us = <1000>;
66 min-residency-us = <2500>;
71 cpu0: cpu@0 {
74 reg = <0x0 0x000>;
75 enable-method = "psci";
76 i-cache-size = <0x8000>;
77 i-cache-line-size = <64>;
78 i-cache-sets = <256>;
79 d-cache-size = <0x8000>;
80 d-cache-line-size = <64>;
81 d-cache-sets = <256>;
82 next-level-cache = <&C0_L2>;
83 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
88 reg = <0x0 0x100>;
89 enable-method = "psci";
90 i-cache-size = <0x8000>;
91 i-cache-line-size = <64>;
92 i-cache-sets = <256>;
93 d-cache-size = <0x8000>;
94 d-cache-line-size = <64>;
95 d-cache-sets = <256>;
96 next-level-cache = <&C0_L2>;
97 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
102 reg = <0x0 0x200>;
103 enable-method = "psci";
104 i-cache-size = <0x8000>;
105 i-cache-line-size = <64>;
106 i-cache-sets = <256>;
107 d-cache-size = <0x8000>;
108 d-cache-line-size = <64>;
109 d-cache-sets = <256>;
110 next-level-cache = <&C0_L2>;
111 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
116 reg = <0x0 0x300>;
117 enable-method = "psci";
118 i-cache-size = <0x8000>;
119 i-cache-line-size = <64>;
120 i-cache-sets = <256>;
121 d-cache-size = <0x8000>;
122 d-cache-line-size = <64>;
123 d-cache-sets = <256>;
124 next-level-cache = <&C0_L2>;
125 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
130 reg = <0x0 0x10000>;
131 enable-method = "psci";
132 i-cache-size = <0x8000>;
133 i-cache-line-size = <64>;
134 i-cache-sets = <256>;
135 d-cache-size = <0x8000>;
136 d-cache-line-size = <64>;
137 d-cache-sets = <256>;
138 next-level-cache = <&C1_L2>;
139 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
144 reg = <0x0 0x10100>;
145 enable-method = "psci";
146 i-cache-size = <0x8000>;
147 i-cache-line-size = <64>;
148 i-cache-sets = <256>;
149 d-cache-size = <0x8000>;
150 d-cache-line-size = <64>;
151 d-cache-sets = <256>;
152 next-level-cache = <&C1_L2>;
153 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
158 reg = <0x0 0x10200>;
159 enable-method = "psci";
160 i-cache-size = <0x8000>;
161 i-cache-line-size = <64>;
162 i-cache-sets = <256>;
163 d-cache-size = <0x8000>;
164 d-cache-line-size = <64>;
165 d-cache-sets = <256>;
166 next-level-cache = <&C1_L2>;
167 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
172 reg = <0x0 0x10300>;
173 enable-method = "psci";
174 i-cache-size = <0x8000>;
175 i-cache-line-size = <64>;
176 i-cache-sets = <256>;
177 d-cache-size = <0x8000>;
178 d-cache-line-size = <64>;
179 d-cache-sets = <256>;
180 next-level-cache = <&C1_L2>;
181 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
183 C0_L2: l2-cache0 {
185 cache-size = <0x80000>;
186 cache-line-size = <64>;
187 cache-sets = <512>;
188 cache-level = <2>;
189 cache-unified;
192 C1_L2: l2-cache1 {
194 cache-size = <0x80000>;
195 cache-line-size = <64>;
196 cache-sets = <512>;
197 cache-level = <2>;
198 cache-unified;
204 reg = <0x00000000 0x80000000 0 0x7c000000>,
205 <0x00000008 0x80000000 0 0x80000000>;
208 reserved-memory {
209 #address-cells = <2>;
210 #size-cells = <2>;
213 /* Chipselect 2,00000000 is physically at 0x18000000 */
216 compatible = "shared-dma-pool";
217 reg = <0x00000000 0x18000000 0 0x00800000>;
218 no-map;
222 gic: interrupt-controller@2f000000 {
223 compatible = "arm,gic-v3";
224 #interrupt-cells = <3>;
225 #address-cells = <2>;
226 #size-cells = <2>;
228 interrupt-controller;
229 reg = <0x0 0x2f000000 0 0x10000>, // GICD
230 <0x0 0x2f100000 0 0x200000>, // GICR
231 <0x0 0x2c000000 0 0x2000>, // GICC
232 <0x0 0x2c010000 0 0x2000>, // GICH
233 <0x0 0x2c02f000 0 0x2000>; // GICV
236 its: msi-controller@2f020000 {
237 #msi-cells = <1>;
238 compatible = "arm,gic-v3-its";
239 reg = <0x0 0x2f020000 0x0 0x20000>; // GITS
240 msi-controller;
245 compatible = "arm,armv8-timer";
253 compatible = "arm,armv7-timer-mem";
254 reg = <0x0 0x2a810000 0x0 0x10000>;
255 ranges = <0 0x0 0x2a820000 0x20000>;
256 #address-cells = <1>;
257 #size-cells = <1>;
259 frame-number = <1>;
261 reg = <0x10000 0x10000>;
266 compatible = "arm,armv8-pmuv3";
270 spe-pmu {
271 compatible = "arm,statistical-profiling-extension-v1";
275 ete-0 {
276 compatible = "arm,embedded-trace-extension";
281 ete-1 {
282 compatible = "arm,embedded-trace-extension";
287 ete-2 {
288 compatible = "arm,embedded-trace-extension";
293 ete-3 {
294 compatible = "arm,embedded-trace-extension";
299 ete-4 {
300 compatible = "arm,embedded-trace-extension";
305 ete-5 {
306 compatible = "arm,embedded-trace-extension";
311 ete-6 {
312 compatible = "arm,embedded-trace-extension";
317 ete-7 {
318 compatible = "arm,embedded-trace-extension";
324 compatible = "arm,trace-buffer-extension";
330 #address-cells = <0x3>;
331 #size-cells = <0x2>;
332 #interrupt-cells = <0x1>;
333 compatible = "pci-host-ecam-generic";
335 bus-range = <0x0 0xff>;
336 reg = <0x0 0x40000000 0x0 0x10000000>;
337 ranges = <0x2000000 0x0 0x50000000 0x0 0x50000000 0x0 0x10000000>;
338 interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
339 <0 0 0 2 &gic 0 0 GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
340 <0 0 0 3 &gic 0 0 GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
341 <0 0 0 4 &gic 0 0 GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
342 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
343 msi-map = <0x0 &its 0x0 0x10000>;
344 iommu-map = <0x0 &smmu 0x0 0x10000>;
346 dma-coherent;
347 ats-supported;
351 compatible = "arm,smmu-v3";
352 reg = <0x0 0x2b400000 0x0 0x100000>;
357 interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";
358 dma-coherent;
359 #iommu-cells = <1>;
360 msi-parent = <&its 0x10000>;
364 compatible = "arm,rtsm-display";
367 remote-endpoint = <&clcd_pads>;
373 #interrupt-cells = <1>;
374 interrupt-map-mask = <0 0 63>;
375 interrupt-map = <0 0 0 &gic 0 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
376 <0 0 1 &gic 0 0 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
377 <0 0 2 &gic 0 0 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
378 <0 0 3 &gic 0 0 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
379 <0 0 4 &gic 0 0 GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
380 <0 0 5 &gic 0 0 GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
381 <0 0 6 &gic 0 0 GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
382 <0 0 7 &gic 0 0 GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
383 <0 0 8 &gic 0 0 GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
384 <0 0 9 &gic 0 0 GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
385 <0 0 10 &gic 0 0 GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
386 <0 0 11 &gic 0 0 GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
387 <0 0 12 &gic 0 0 GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
388 <0 0 13 &gic 0 0 GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
389 <0 0 14 &gic 0 0 GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
390 <0 0 15 &gic 0 0 GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
391 <0 0 16 &gic 0 0 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
392 <0 0 17 &gic 0 0 GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
393 <0 0 18 &gic 0 0 GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
394 <0 0 19 &gic 0 0 GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
395 <0 0 20 &gic 0 0 GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
396 <0 0 21 &gic 0 0 GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
397 <0 0 22 &gic 0 0 GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
398 <0 0 23 &gic 0 0 GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
399 <0 0 24 &gic 0 0 GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
400 <0 0 25 &gic 0 0 GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
401 <0 0 26 &gic 0 0 GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
402 <0 0 27 &gic 0 0 GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
403 <0 0 28 &gic 0 0 GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
404 <0 0 29 &gic 0 0 GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
405 <0 0 30 &gic 0 0 GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
406 <0 0 31 &gic 0 0 GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
407 <0 0 32 &gic 0 0 GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
408 <0 0 33 &gic 0 0 GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
409 <0 0 34 &gic 0 0 GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
410 <0 0 35 &gic 0 0 GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
411 <0 0 36 &gic 0 0 GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
412 <0 0 37 &gic 0 0 GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
413 <0 0 38 &gic 0 0 GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
414 <0 0 39 &gic 0 0 GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
415 <0 0 40 &gic 0 0 GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
416 <0 0 41 &gic 0 0 GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
417 <0 0 42 &gic 0 0 GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
418 <0 0 43 &gic 0 0 GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
419 <0 0 44 &gic 0 0 GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
420 <0 0 46 &gic 0 0 GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;