Lines Matching +full:0 +full:x3b100000
23 #size-cells = <0>;
57 cpu_e0: cpu@0 {
60 reg = <0x0 0x0>;
62 cpu-release-addr = <0 0>; /* To be filled by loader */
67 i-cache-size = <0x20000>;
68 d-cache-size = <0x10000>;
74 reg = <0x0 0x1>;
76 cpu-release-addr = <0 0>; /* To be filled by loader */
81 i-cache-size = <0x20000>;
82 d-cache-size = <0x10000>;
88 reg = <0x0 0x2>;
90 cpu-release-addr = <0 0>; /* To be filled by loader */
95 i-cache-size = <0x20000>;
96 d-cache-size = <0x10000>;
102 reg = <0x0 0x3>;
104 cpu-release-addr = <0 0>; /* To be filled by loader */
109 i-cache-size = <0x20000>;
110 d-cache-size = <0x10000>;
116 reg = <0x0 0x10100>;
118 cpu-release-addr = <0 0>; /* To be filled by loader */
123 i-cache-size = <0x30000>;
124 d-cache-size = <0x20000>;
130 reg = <0x0 0x10101>;
132 cpu-release-addr = <0 0>; /* To be filled by loader */
137 i-cache-size = <0x30000>;
138 d-cache-size = <0x20000>;
144 reg = <0x0 0x10102>;
146 cpu-release-addr = <0 0>; /* To be filled by loader */
151 i-cache-size = <0x30000>;
152 d-cache-size = <0x20000>;
158 reg = <0x0 0x10103>;
160 cpu-release-addr = <0 0>; /* To be filled by loader */
165 i-cache-size = <0x30000>;
166 d-cache-size = <0x20000>;
169 l2_cache_0: l2-cache-0 {
173 cache-size = <0x400000>;
180 cache-size = <0xc00000>;
184 ecluster_opp: opp-table-0 {
277 #if 0
324 #clock-cells = <0>;
335 #clock-cells = <0>;
349 reg = <0x2 0x10e20000 0 0x1000>;
350 #performance-domain-cells = <0>;
355 reg = <0x2 0x11e20000 0 0x1000>;
356 #performance-domain-cells = <0>;
361 reg = <0x2 0x35004000 0x0 0x4000>;
370 reg = <0x2 0x35010000 0x0 0x4000>;
374 pinctrl-0 = <&i2c0_pins>;
376 #address-cells = <0x1>;
377 #size-cells = <0x0>;
383 reg = <0x2 0x35014000 0x0 0x4000>;
387 pinctrl-0 = <&i2c1_pins>;
389 #address-cells = <0x1>;
390 #size-cells = <0x0>;
396 reg = <0x2 0x35018000 0x0 0x4000>;
400 pinctrl-0 = <&i2c2_pins>;
402 #address-cells = <0x1>;
403 #size-cells = <0x0>;
410 reg = <0x2 0x3501c000 0x0 0x4000>;
414 pinctrl-0 = <&i2c3_pins>;
416 #address-cells = <0x1>;
417 #size-cells = <0x0>;
423 reg = <0x2 0x35020000 0x0 0x4000>;
427 pinctrl-0 = <&i2c4_pins>;
429 #address-cells = <0x1>;
430 #size-cells = <0x0>;
437 reg = <0x2 0x35044000 0x0 0x4000>;
446 reg = <0x2 0x35200000 0x0 0x1000>;
462 reg = <0x2 0x35208000 0x0 0x1000>;
474 reg = <0x2 0x38200000 0x0 0x34000>;
476 interrupts-extended = <0>,
478 <0>,
479 <0>;
488 reg = <0x2 0x38400000 0x0 0x18000>,
489 <0x2 0x38300000 0x0 0x30000>;
500 clocks = <&nco 0>, <&nco 1>, <&nco 2>,
504 dmas = <&admac 0>, <&admac 1>, <&admac 2>, <&admac 3>,
522 reg = <0x2 0x3b044000 0x0 0x14000>;
531 reg = <0x2 0x3b100000 0x0 0x8000>;
551 reg = <0x2 0x3b700000 0 0x14000>;
556 reg = <0x2 0x3c100000 0x0 0x100000>;
561 gpio-ranges = <&pinctrl_ap 0 0 212>;
609 reg = <0x2 0x3d1f0000 0x0 0x4000>;
614 gpio-ranges = <&pinctrl_nub 0 0 23>;
633 reg = <0x2 0x3d280000 0 0x4000>;
638 reg = <0x2 0x3d2b0000 0x0 0x4000>;
646 reg = <0x2 0x3e820000 0x0 0x4000>;
650 gpio-ranges = <&pinctrl_smc 0 0 16>;
667 reg = <0x2 0x4a820000 0x0 0x4000>;
671 gpio-ranges = <&pinctrl_aop 0 0 42>;
688 reg = <0x2 0x77408000 0x0 0x4000>;
696 #mbox-cells = <0>;
702 reg = <0x2 0x7bc50000 0x0 0x10000>;
708 reg = <0x2 0x7bcc0000 0x0 0x40000>,
709 <0x2 0x77400000 0x0 0x4000>;
722 reg = <0x6 0x81008000 0x0 0x4000>;
731 reg = <0x6 0x82008000 0x0 0x4000>;
741 reg = <0x6 0x83008000 0x0 0x4000>;
753 reg = <0x6 0x90000000 0x0 0x1000000>,
754 <0x6 0x80000000 0x0 0x100000>,
755 <0x6 0x81000000 0x0 0x4000>,
756 <0x6 0x82000000 0x0 0x4000>,
757 <0x6 0x83000000 0x0 0x4000>;
770 iommu-map = <0x100 &pcie0_dart_0 1 1>,
771 <0x200 &pcie0_dart_1 1 1>,
772 <0x300 &pcie0_dart_2 1 1>;
773 iommu-map-mask = <0xff00>;
775 bus-range = <0 3>;
778 ranges = <0x43000000 0x6 0xa0000000 0x6 0xa0000000 0x0 0x20000000>,
779 <0x02000000 0x0 0xc0000000 0x6 0xc0000000 0x0 0x40000000>;
782 pinctrl-0 = <&pcie_pins>;
785 port00: pci@0,0 {
787 reg = <0x0 0x0 0x0 0x0 0x0>;
797 interrupt-map-mask = <0 0 0 7>;
798 interrupt-map = <0 0 0 1 &port00 0 0 0 0>,
799 <0 0 0 2 &port00 0 0 0 1>,
800 <0 0 0 3 &port00 0 0 0 2>,
801 <0 0 0 4 &port00 0 0 0 3>;
804 port01: pci@1,0 {
806 reg = <0x800 0x0 0x0 0x0 0x0>;
816 interrupt-map-mask = <0 0 0 7>;
817 interrupt-map = <0 0 0 1 &port01 0 0 0 0>,
818 <0 0 0 2 &port01 0 0 0 1>,
819 <0 0 0 3 &port01 0 0 0 2>,
820 <0 0 0 4 &port01 0 0 0 3>;
824 port02: pci@2,0 {
826 reg = <0x1000 0x0 0x0 0x0 0x0>;
836 interrupt-map-mask = <0 0 0 7>;
837 interrupt-map = <0 0 0 1 &port02 0 0 0 0>,
838 <0 0 0 2 &port02 0 0 0 1>,
839 <0 0 0 3 &port02 0 0 0 2>,
840 <0 0 0 4 &port02 0 0 0 3>;