Lines Matching +full:opp +full:- +full:level
1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/interrupt-controller/apple-aic.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/pinctrl/apple.h>
16 interrupt-parent = <&aic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
20 clkref: clock-ref {
21 compatible = "fixed-clock";
22 #clock-cells = <0>;
23 clock-frequency = <24000000>;
24 clock-output-names = "clkref";
28 #address-cells = <2>;
29 #size-cells = <0>;
32 compatible = "apple,hurricane-zephyr";
34 cpu-release-addr = <0 0>; /* To be filled by loader */
35 operating-points-v2 = <&fusion_opp>;
36 performance-domains = <&cpufreq>;
37 enable-method = "spin-table";
39 next-level-cache = <&l2_cache>;
40 i-cache-size = <0x10000>; /* P-core */
41 d-cache-size = <0x10000>; /* P-core */
45 compatible = "apple,hurricane-zephyr";
47 cpu-release-addr = <0 0>; /* To be filled by loader */
48 operating-points-v2 = <&fusion_opp>;
49 performance-domains = <&cpufreq>;
50 enable-method = "spin-table";
52 next-level-cache = <&l2_cache>;
53 i-cache-size = <0x10000>; /* P-core */
54 d-cache-size = <0x10000>; /* P-core */
58 compatible = "apple,hurricane-zephyr";
60 cpu-release-addr = <0 0>; /* To be filled by loader */
61 operating-points-v2 = <&fusion_opp>;
62 performance-domains = <&cpufreq>;
63 enable-method = "spin-table";
65 next-level-cache = <&l2_cache>;
66 i-cache-size = <0x10000>; /* P-core */
67 d-cache-size = <0x10000>; /* P-core */
70 l2_cache: l2-cache {
72 cache-level = <2>;
73 cache-unified;
74 cache-size = <0x800000>; /* P-cluster */
78 fusion_opp: opp-table {
79 compatible = "operating-points-v2";
83 * that use p-state transitions to switch between cores.
85 * The E-core frequencies are adjusted so performance scales
90 opp-hz = /bits/ 64 <172000000>; /* 300 MHz, E-core */
91 opp-level = <1>;
92 clock-latency-ns = <12000>;
95 opp-hz = /bits/ 64 <230000000>; /* 396 MHz, E-core */
96 opp-level = <2>;
97 clock-latency-ns = <135000>;
100 opp-hz = /bits/ 64 <448000000>; /* 768 MHz, E-core */
101 opp-level = <3>;
102 clock-latency-ns = <105000>;
105 opp-hz = /bits/ 64 <662000000>; /* 1152 MHz, E-core */
106 opp-level = <4>;
107 clock-latency-ns = <115000>;
110 opp-hz = /bits/ 64 <804000000>;
111 opp-level = <5>;
112 clock-latency-ns = <122000>;
115 opp-hz = /bits/ 64 <1140000000>;
116 opp-level = <6>;
117 clock-latency-ns = <120000>;
120 opp-hz = /bits/ 64 <1548000000>;
121 opp-level = <7>;
122 clock-latency-ns = <125000>;
125 opp-hz = /bits/ 64 <1956000000>;
126 opp-level = <8>;
127 clock-latency-ns = <135000>;
130 opp-hz = /bits/ 64 <2316000000>;
131 opp-level = <9>;
132 clock-latency-ns = <140000>;
137 opp-hz = /bits/ 64 <2400000000>;
138 opp-level = <10>;
139 clock-latency-ns = <140000>;
140 turbo-mode;
146 compatible = "simple-bus";
147 #address-cells = <2>;
148 #size-cells = <2>;
149 nonposted-mmio;
152 cpufreq: performance-controller@202f20000 {
153 …compatible = "apple,t8010-cluster-cpufreq", "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq";
155 #performance-domain-cells = <0>;
159 compatible = "apple,s5l-uart";
161 reg-io-width = <4>;
162 interrupt-parent = <&aic>;
164 /* Use the bootloader-enabled clocks for now. */
166 clock-names = "uart", "clk_uart_baud0";
167 power-domains = <&ps_uart0>;
171 pmgr: power-management@20e000000 {
172 compatible = "apple,t8010-pmgr", "apple,pmgr", "syscon", "simple-mfd";
173 #address-cells = <1>;
174 #size-cells = <1>;
179 aic: interrupt-controller@20e100000 {
180 compatible = "apple,t8010-aic", "apple,aic";
182 #interrupt-cells = <3>;
183 interrupt-controller;
184 power-domains = <&ps_aic>;
188 compatible = "apple,t8010-pinctrl", "apple,pinctrl";
190 power-domains = <&ps_gpio>;
192 gpio-controller;
193 #gpio-cells = <2>;
194 gpio-ranges = <&pinctrl_ap 0 0 219>;
197 interrupt-controller;
198 #interrupt-cells = <2>;
199 interrupt-parent = <&aic>;
210 compatible = "apple,t8010-pinctrl", "apple,pinctrl";
212 power-domains = <&ps_aop_gpio>;
214 gpio-controller;
215 #gpio-cells = <2>;
216 gpio-ranges = <&pinctrl_aop 0 0 42>;
219 interrupt-controller;
220 #interrupt-cells = <2>;
221 interrupt-parent = <&aic>;
231 pmgr_mini: power-management@210200000 {
232 compatible = "apple,t8010-pmgr", "apple,pmgr", "syscon", "simple-mfd";
233 #address-cells = <1>;
234 #size-cells = <1>;
240 compatible = "apple,t8010-wdt", "apple,wdt";
243 interrupt-parent = <&aic>;
249 compatible = "arm,armv8-timer";
250 interrupt-parent = <&aic>;
251 interrupt-names = "phys", "virt";
258 #include "t8011-pmgr.dtsi"