Lines Matching +full:opp +full:- +full:level
1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interrupt-controller/apple-aic.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/pinctrl/apple.h>
15 interrupt-parent = <&aic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
23 clkref: clock-ref {
24 compatible = "fixed-clock";
25 #clock-cells = <0>;
26 clock-frequency = <24000000>;
27 clock-output-names = "clkref";
31 #address-cells = <2>;
32 #size-cells = <0>;
37 cpu-release-addr = <0 0>; /* To be filled in by loader */
38 performance-domains = <&cpufreq>;
39 operating-points-v2 = <&typhoon_opp>;
40 enable-method = "spin-table";
42 next-level-cache = <&l2_cache>;
43 i-cache-size = <0x10000>;
44 d-cache-size = <0x10000>;
50 cpu-release-addr = <0 0>; /* To be filled in by loader */
51 performance-domains = <&cpufreq>;
52 operating-points-v2 = <&typhoon_opp>;
53 enable-method = "spin-table";
55 next-level-cache = <&l2_cache>;
56 i-cache-size = <0x10000>;
57 d-cache-size = <0x10000>;
63 cpu-release-addr = <0 0>; /* To be filled by loader */
64 performance-domains = <&cpufreq>;
65 operating-points-v2 = <&typhoon_opp>;
66 enable-method = "spin-table";
68 next-level-cache = <&l2_cache>;
69 i-cache-size = <0x10000>;
70 d-cache-size = <0x10000>;
73 l2_cache: l2-cache {
75 cache-level = <2>;
76 cache-unified;
77 cache-size = <0x200000>;
81 typhoon_opp: opp-table {
82 compatible = "operating-points-v2";
85 opp-hz = /bits/ 64 <300000000>;
86 opp-level = <1>;
87 clock-latency-ns = <300>;
90 opp-hz = /bits/ 64 <396000000>;
91 opp-level = <2>;
92 clock-latency-ns = <49000>;
95 opp-hz = /bits/ 64 <600000000>;
96 opp-level = <3>;
97 clock-latency-ns = <31000>;
100 opp-hz = /bits/ 64 <840000000>;
101 opp-level = <4>;
102 clock-latency-ns = <32000>;
105 opp-hz = /bits/ 64 <1128000000>;
106 opp-level = <5>;
107 clock-latency-ns = <32000>;
110 opp-hz = /bits/ 64 <1392000000>;
111 opp-level = <6>;
112 clock-latency-ns = <37000>;
115 opp-hz = /bits/ 64 <1512000000>;
116 opp-level = <7>;
117 clock-latency-ns = <41000>;
122 compatible = "simple-bus";
123 #address-cells = <2>;
124 #size-cells = <2>;
125 nonposted-mmio;
128 cpufreq: performance-controller@202220000 {
129 compatible = "apple,t7000-cluster-cpufreq", "apple,s5l8960x-cluster-cpufreq";
131 #performance-domain-cells = <0>;
135 compatible = "apple,s5l-uart";
137 reg-io-width = <4>;
138 interrupt-parent = <&aic>;
140 /* Use the bootloader-enabled clocks for now. */
142 clock-names = "uart", "clk_uart_baud0";
143 power-domains = <&ps_uart0>;
147 pmgr: power-management@20e000000 {
148 compatible = "apple,t7000-pmgr", "apple,pmgr", "syscon", "simple-mfd";
149 #address-cells = <1>;
150 #size-cells = <1>;
156 compatible = "apple,t7000-wdt", "apple,wdt";
159 interrupt-parent = <&aic>;
163 aic: interrupt-controller@20e100000 {
164 compatible = "apple,t7000-aic", "apple,aic";
166 #interrupt-cells = <3>;
167 interrupt-controller;
168 power-domains = <&ps_aic>;
172 compatible = "apple,t7000-pinctrl", "apple,pinctrl";
174 power-domains = <&ps_gpio>;
176 gpio-controller;
177 #gpio-cells = <2>;
178 gpio-ranges = <&pinctrl 0 0 184>;
181 interrupt-controller;
182 #interrupt-cells = <2>;
183 interrupt-parent = <&aic>;
195 compatible = "arm,armv8-timer";
196 interrupt-parent = <&aic>;
197 interrupt-names = "phys", "virt";
204 #include "t7001-pmgr.dtsi"