Lines Matching +full:opp +full:- +full:0
1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
11 #address-cells = <2>;
12 #size-cells = <2>;
15 #address-cells = <2>;
16 #size-cells = <0>;
18 cpu-map {
59 cpu_e00: cpu@0 {
62 reg = <0x0 0x0>;
63 enable-method = "spin-table";
64 cpu-release-addr = <0 0>; /* To be filled by loader */
65 next-level-cache = <&l2_cache_0>;
66 i-cache-size = <0x20000>;
67 d-cache-size = <0x10000>;
68 operating-points-v2 = <&icestorm_opp>;
69 capacity-dmips-mhz = <714>;
70 performance-domains = <&cpufreq_e>;
76 reg = <0x0 0x1>;
77 enable-method = "spin-table";
78 cpu-release-addr = <0 0>; /* To be filled by loader */
79 next-level-cache = <&l2_cache_0>;
80 i-cache-size = <0x20000>;
81 d-cache-size = <0x10000>;
82 operating-points-v2 = <&icestorm_opp>;
83 capacity-dmips-mhz = <714>;
84 performance-domains = <&cpufreq_e>;
90 reg = <0x0 0x10100>;
91 enable-method = "spin-table";
92 cpu-release-addr = <0 0>; /* To be filled by loader */
93 next-level-cache = <&l2_cache_1>;
94 i-cache-size = <0x30000>;
95 d-cache-size = <0x20000>;
96 operating-points-v2 = <&firestorm_opp>;
97 capacity-dmips-mhz = <1024>;
98 performance-domains = <&cpufreq_p0>;
104 reg = <0x0 0x10101>;
105 enable-method = "spin-table";
106 cpu-release-addr = <0 0>; /* To be filled by loader */
107 next-level-cache = <&l2_cache_1>;
108 i-cache-size = <0x30000>;
109 d-cache-size = <0x20000>;
110 operating-points-v2 = <&firestorm_opp>;
111 capacity-dmips-mhz = <1024>;
112 performance-domains = <&cpufreq_p0>;
118 reg = <0x0 0x10102>;
119 enable-method = "spin-table";
120 cpu-release-addr = <0 0>; /* To be filled by loader */
121 next-level-cache = <&l2_cache_1>;
122 i-cache-size = <0x30000>;
123 d-cache-size = <0x20000>;
124 operating-points-v2 = <&firestorm_opp>;
125 capacity-dmips-mhz = <1024>;
126 performance-domains = <&cpufreq_p0>;
132 reg = <0x0 0x10103>;
133 enable-method = "spin-table";
134 cpu-release-addr = <0 0>; /* To be filled by loader */
135 next-level-cache = <&l2_cache_1>;
136 i-cache-size = <0x30000>;
137 d-cache-size = <0x20000>;
138 operating-points-v2 = <&firestorm_opp>;
139 capacity-dmips-mhz = <1024>;
140 performance-domains = <&cpufreq_p0>;
146 reg = <0x0 0x10200>;
147 enable-method = "spin-table";
148 cpu-release-addr = <0 0>; /* To be filled by loader */
149 next-level-cache = <&l2_cache_2>;
150 i-cache-size = <0x30000>;
151 d-cache-size = <0x20000>;
152 operating-points-v2 = <&firestorm_opp>;
153 capacity-dmips-mhz = <1024>;
154 performance-domains = <&cpufreq_p1>;
160 reg = <0x0 0x10201>;
161 enable-method = "spin-table";
162 cpu-release-addr = <0 0>; /* To be filled by loader */
163 next-level-cache = <&l2_cache_2>;
164 i-cache-size = <0x30000>;
165 d-cache-size = <0x20000>;
166 operating-points-v2 = <&firestorm_opp>;
167 capacity-dmips-mhz = <1024>;
168 performance-domains = <&cpufreq_p1>;
174 reg = <0x0 0x10202>;
175 enable-method = "spin-table";
176 cpu-release-addr = <0 0>; /* To be filled by loader */
177 next-level-cache = <&l2_cache_2>;
178 i-cache-size = <0x30000>;
179 d-cache-size = <0x20000>;
180 operating-points-v2 = <&firestorm_opp>;
181 capacity-dmips-mhz = <1024>;
182 performance-domains = <&cpufreq_p1>;
188 reg = <0x0 0x10203>;
189 enable-method = "spin-table";
190 cpu-release-addr = <0 0>; /* To be filled by loader */
191 next-level-cache = <&l2_cache_2>;
192 i-cache-size = <0x30000>;
193 d-cache-size = <0x20000>;
194 operating-points-v2 = <&firestorm_opp>;
195 capacity-dmips-mhz = <1024>;
196 performance-domains = <&cpufreq_p1>;
199 l2_cache_0: l2-cache-0 {
201 cache-level = <2>;
202 cache-unified;
203 cache-size = <0x400000>;
206 l2_cache_1: l2-cache-1 {
208 cache-level = <2>;
209 cache-unified;
210 cache-size = <0xc00000>;
213 l2_cache_2: l2-cache-2 {
215 cache-level = <2>;
216 cache-unified;
217 cache-size = <0xc00000>;
221 icestorm_opp: opp-table-0 {
222 compatible = "operating-points-v2";
225 opp-hz = /bits/ 64 <600000000>;
226 opp-level = <1>;
227 clock-latency-ns = <7500>;
230 opp-hz = /bits/ 64 <972000000>;
231 opp-level = <2>;
232 clock-latency-ns = <23000>;
235 opp-hz = /bits/ 64 <1332000000>;
236 opp-level = <3>;
237 clock-latency-ns = <29000>;
240 opp-hz = /bits/ 64 <1704000000>;
241 opp-level = <4>;
242 clock-latency-ns = <40000>;
245 opp-hz = /bits/ 64 <2064000000>;
246 opp-level = <5>;
247 clock-latency-ns = <50000>;
251 firestorm_opp: opp-table-1 {
252 compatible = "operating-points-v2";
255 opp-hz = /bits/ 64 <600000000>;
256 opp-level = <1>;
257 clock-latency-ns = <8000>;
260 opp-hz = /bits/ 64 <828000000>;
261 opp-level = <2>;
262 clock-latency-ns = <18000>;
265 opp-hz = /bits/ 64 <1056000000>;
266 opp-level = <3>;
267 clock-latency-ns = <19000>;
270 opp-hz = /bits/ 64 <1296000000>;
271 opp-level = <4>;
272 clock-latency-ns = <23000>;
275 opp-hz = /bits/ 64 <1524000000>;
276 opp-level = <5>;
277 clock-latency-ns = <24000>;
280 opp-hz = /bits/ 64 <1752000000>;
281 opp-level = <6>;
282 clock-latency-ns = <28000>;
285 opp-hz = /bits/ 64 <1980000000>;
286 opp-level = <7>;
287 clock-latency-ns = <31000>;
290 opp-hz = /bits/ 64 <2208000000>;
291 opp-level = <8>;
292 clock-latency-ns = <45000>;
295 opp-hz = /bits/ 64 <2448000000>;
296 opp-level = <9>;
297 clock-latency-ns = <49000>;
300 opp-hz = /bits/ 64 <2676000000>;
301 opp-level = <10>;
302 clock-latency-ns = <53000>;
305 opp-hz = /bits/ 64 <2904000000>;
306 opp-level = <11>;
307 clock-latency-ns = <56000>;
310 opp-hz = /bits/ 64 <3036000000>;
311 opp-level = <12>;
312 clock-latency-ns = <56000>;
316 opp-hz = /bits/ 64 <3132000000>;
317 opp-level = <13>;
318 clock-latency-ns = <56000>;
319 turbo-mode;
322 opp-hz = /bits/ 64 <3168000000>;
323 opp-level = <14>;
324 clock-latency-ns = <56000>;
325 turbo-mode;
328 opp-hz = /bits/ 64 <3228000000>;
329 opp-level = <15>;
330 clock-latency-ns = <56000>;
331 turbo-mode;
336 pmu-e {
337 compatible = "apple,icestorm-pmu";
338 interrupt-parent = <&aic>;
339 interrupts = <AIC_FIQ 0 AIC_CPU_PMU_E IRQ_TYPE_LEVEL_HIGH>;
342 pmu-p {
343 compatible = "apple,firestorm-pmu";
344 interrupt-parent = <&aic>;
345 interrupts = <AIC_FIQ 0 AIC_CPU_PMU_P IRQ_TYPE_LEVEL_HIGH>;
349 compatible = "arm,armv8-timer";
350 interrupt-parent = <&aic>;
351 interrupt-names = "phys", "virt", "hyp-phys", "hyp-virt";
352 interrupts = <AIC_FIQ 0 AIC_TMR_GUEST_PHYS IRQ_TYPE_LEVEL_HIGH>,
353 <AIC_FIQ 0 AIC_TMR_GUEST_VIRT IRQ_TYPE_LEVEL_HIGH>,
354 <AIC_FIQ 0 AIC_TMR_HV_PHYS IRQ_TYPE_LEVEL_HIGH>,
355 <AIC_FIQ 0 AIC_TMR_HV_VIRT IRQ_TYPE_LEVEL_HIGH>;
358 clkref: clock-ref {
359 compatible = "fixed-clock";
360 #clock-cells = <0>;
361 clock-frequency = <24000000>;
362 clock-output-names = "clkref";
369 nco_clkref: clock-ref-nco {
370 compatible = "fixed-clock";
371 #clock-cells = <0>;
372 clock-output-names = "nco_ref";