Lines Matching +full:0 +full:xc300
16 #size-cells = <0>;
18 cpu@0 {
21 reg = <0x0 0x000>;
23 cpu-release-addr = <0x1 0x0000fff8>;
29 reg = <0x0 0x001>;
31 cpu-release-addr = <0x1 0x0000fff8>;
37 reg = <0x0 0x100>;
39 cpu-release-addr = <0x1 0x0000fff8>;
45 reg = <0x0 0x101>;
47 cpu-release-addr = <0x1 0x0000fff8>;
53 reg = <0x0 0x200>;
55 cpu-release-addr = <0x1 0x0000fff8>;
61 reg = <0x0 0x201>;
63 cpu-release-addr = <0x1 0x0000fff8>;
69 reg = <0x0 0x300>;
71 cpu-release-addr = <0x1 0x0000fff8>;
77 reg = <0x0 0x301>;
79 cpu-release-addr = <0x1 0x0000fff8>;
82 xgene_L2_0: l2-cache-0 {
108 reg = <0x0 0x78010000 0x0 0x1000>, /* GIC Dist */
109 <0x0 0x78020000 0x0 0x1000>, /* GIC CPU */
110 <0x0 0x78040000 0x0 0x2000>, /* GIC VCPU Control */
111 <0x0 0x78060000 0x0 0x2000>; /* GIC VCPU */
112 interrupts = <1 9 0xf04>; /* GIC Maintenence IRQ */
117 interrupts = <1 0 0xff08>, /* Secure Phys IRQ */
118 <1 13 0xff08>, /* Non-secure Phys IRQ */
119 <1 14 0xff08>, /* Virt IRQ */
120 <1 15 0xff08>; /* Hyp IRQ */
126 interrupts = <1 12 0xff04>;
134 dma-ranges = <0x0 0x0 0x0 0x0 0x400 0x0>;
150 clocks = <&refclk 0>;
152 reg = <0x0 0x17000100 0x0 0x1000>;
154 type = <0>;
160 clocks = <&refclk 0>;
162 reg = <0x0 0x17000120 0x0 0x1000>;
170 clocks = <&socpll 0>;
180 clocks = <&socplldiv2 0>;
181 reg = <0x0 0x17000000 0x0 0x2000>;
183 divider-offset = <0x164>;
184 divider-width = <0x5>;
185 divider-shift = <0x0>;
192 clocks = <&socplldiv2 0>;
193 reg = <0x0 0x1f2ac000 0x0 0x1000
194 0x0 0x17000000 0x0 0x2000>;
196 csr-offset = <0x0>;
197 csr-mask = <0x2>;
198 enable-offset = <0x8>;
199 enable-mask = <0x2>;
200 divider-offset = <0x178>;
201 divider-width = <0x8>;
202 divider-shift = <0x0>;
209 clocks = <&socplldiv2 0>;
211 reg = <0x0 0x17000000 0x0 0x1000>;
213 divider-offset = <0x238>;
214 divider-width = <0x9>;
215 divider-shift = <0x0>;
222 clocks = <ðclk 0>;
223 reg = <0x0 0x1702c000 0x0 0x1000>;
231 clocks = <&socplldiv2 0>;
232 reg = <0x0 0x1f21c000 0x0 0x1000>;
234 csr-mask = <0xa>;
235 enable-mask = <0xf>;
242 clocks = <&socplldiv2 0>;
243 reg = <0x0 0x1f61c000 0x0 0x1000>;
245 csr-mask = <0x3>;
253 clocks = <&socplldiv2 0>;
254 reg = <0x0 0x1f62c000 0x0 0x1000>;
256 csr-mask = <0x3>;
263 clocks = <&socplldiv2 0>;
264 reg = <0x0 0x1f21c000 0x0 0x1000>;
268 csr-offset = <0x4>;
269 csr-mask = <0x00>;
270 enable-offset = <0x0>;
271 enable-mask = <0x06>;
277 clocks = <&socplldiv2 0>;
278 reg = <0x0 0x1f22c000 0x0 0x1000>;
282 csr-offset = <0x4>;
283 csr-mask = <0x3a>;
284 enable-offset = <0x0>;
285 enable-mask = <0x06>;
291 clocks = <&socplldiv2 0>;
292 reg = <0x0 0x1f23c000 0x0 0x1000>;
296 csr-offset = <0x4>;
297 csr-mask = <0x3a>;
298 enable-offset = <0x0>;
299 enable-mask = <0x06>;
305 clocks = <&socplldiv2 0>;
306 reg = <0x0 0x1f21c000 0x0 0x1000>;
309 csr-offset = <0x4>;
310 csr-mask = <0x05>;
311 enable-offset = <0x0>;
312 enable-mask = <0x39>;
318 clocks = <&socplldiv2 0>;
319 reg = <0x0 0x1f22c000 0x0 0x1000>;
322 csr-offset = <0x4>;
323 csr-mask = <0x05>;
324 enable-offset = <0x0>;
325 enable-mask = <0x39>;
331 clocks = <&socplldiv2 0>;
332 reg = <0x0 0x1f23c000 0x0 0x1000>;
335 csr-offset = <0x4>;
336 csr-mask = <0x05>;
337 enable-offset = <0x0>;
338 enable-mask = <0x39>;
344 clocks = <&socplldiv2 0>;
345 reg = <0x0 0x17000000 0x0 0x2000>;
347 csr-offset = <0xc>;
348 csr-mask = <0x2>;
349 enable-offset = <0x10>;
350 enable-mask = <0x2>;
357 clocks = <&socplldiv2 0>;
358 reg = <0x0 0x17000000 0x0 0x2000>;
360 csr-offset = <0xc>;
361 csr-mask = <0x10>;
362 enable-offset = <0x10>;
363 enable-mask = <0x10>;
371 clocks = <&socplldiv2 0>;
372 reg = <0x0 0x1f2bc000 0x0 0x1000>;
381 clocks = <&socplldiv2 0>;
382 reg = <0x0 0x1f2cc000 0x0 0x1000>;
391 clocks = <&socplldiv2 0>;
392 reg = <0x0 0x1f2dc000 0x0 0x1000>;
401 clocks = <&socplldiv2 0>;
402 reg = <0x0 0x1f50c000 0x0 0x1000>;
411 clocks = <&socplldiv2 0>;
412 reg = <0x0 0x1f51c000 0x0 0x1000>;
420 clocks = <&socplldiv2 0>;
421 reg = <0x0 0x1f27c000 0x0 0x1000>;
430 reg = <0x00 0x79000000 0x0 0x900000>;
431 interrupts = < 0x0 0x10 0x4
432 0x0 0x11 0x4
433 0x0 0x12 0x4
434 0x0 0x13 0x4
435 0x0 0x14 0x4
436 0x0 0x15 0x4
437 0x0 0x16 0x4
438 0x0 0x17 0x4
439 0x0 0x18 0x4
440 0x0 0x19 0x4
441 0x0 0x1a 0x4
442 0x0 0x1b 0x4
443 0x0 0x1c 0x4
444 0x0 0x1d 0x4
445 0x0 0x1e 0x4
446 0x0 0x1f 0x4>;
451 reg = <0x0 0x17000000 0x0 0x400>;
457 offset = <0x14>;
458 mask = <0x1>;
463 reg = <0x0 0x7e200000 0x0 0x1000>;
468 reg = <0x0 0x7e700000 0x0 0x1000>;
473 reg = <0x0 0x7e720000 0x0 0x1000>;
478 reg = <0x0 0x1054a000 0x0 0x20>;
483 reg = <0x0 0x7e000000 0x0 0x10>;
496 reg = <0x0 0x78800000 0x0 0x100>;
497 interrupts = <0x0 0x20 0x4>,
498 <0x0 0x21 0x4>,
499 <0x0 0x27 0x4>;
503 reg = <0x0 0x7e800000 0x0 0x1000>;
504 memory-controller = <0>;
509 reg = <0x0 0x7e840000 0x0 0x1000>;
515 reg = <0x0 0x7e880000 0x0 0x1000>;
521 reg = <0x0 0x7e8c0000 0x0 0x1000>;
527 reg = <0x0 0x7c000000 0x0 0x200000>;
528 pmd-controller = <0>;
533 reg = <0x0 0x7c200000 0x0 0x200000>;
539 reg = <0x0 0x7c400000 0x0 0x200000>;
545 reg = <0x0 0x7c600000 0x0 0x200000>;
551 reg = <0x0 0x7e600000 0x0 0x1000>;
556 reg = <0x0 0x7e930000 0x0 0x1000>;
568 reg = <0x0 0x78810000 0x0 0x1000>;
569 interrupts = <0x0 0x22 0x4>;
573 reg = <0x0 0x7e610000 0x0 0x1000>;
578 reg = <0x0 0x7e940000 0x0 0x1000>;
583 reg = <0x0 0x7e710000 0x0 0x1000>;
584 enable-bit-index = <0>;
589 reg = <0x0 0x7e730000 0x0 0x1000>;
595 reg = <0x0 0x7e810000 0x0 0x1000>;
596 enable-bit-index = <0>;
601 reg = <0x0 0x7e850000 0x0 0x1000>;
607 reg = <0x0 0x7e890000 0x0 0x1000>;
613 reg = <0x0 0x7e8d0000 0x0 0x1000>;
625 reg = < 0x00 0x1f2b0000 0x0 0x00010000 /* Controller registers */
626 0xe0 0xd0000000 0x0 0x00040000>; /* PCI config space */
628 ranges = <0x01000000 0x00 0x00000000 0xe0 0x10000000 0x00 0x00010000 /* io */
629 0x02000000 0x00 0x80000000 0xe1 0x80000000 0x00 0x80000000 /* mem */
630 0x43000000 0xf0 0x00000000 0xf0 0x00000000 0x10 0x00000000>; /* mem */
631 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
632 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
633 bus-range = <0x00 0xff>;
634 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
635 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc2 0x4
636 0x0 0x0 0x0 0x2 &gic 0x0 0xc3 0x4
637 0x0 0x0 0x0 0x3 &gic 0x0 0xc4 0x4
638 0x0 0x0 0x0 0x4 &gic 0x0 0xc5 0x4>;
640 clocks = <&pcie0clk 0>;
651 reg = < 0x00 0x1f2c0000 0x0 0x00010000 /* Controller registers */
652 0xd0 0xd0000000 0x0 0x00040000>; /* PCI config space */
654 ranges = <0x01000000 0x00 0x00000000 0xd0 0x10000000 0x00 0x00010000 /* io */
655 0x02000000 0x00 0x80000000 0xd1 0x80000000 0x00 0x80000000 /* mem */
656 0x43000000 0xd8 0x00000000 0xd8 0x00000000 0x08 0x00000000>; /* mem */
657 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
658 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
659 bus-range = <0x00 0xff>;
660 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
661 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc8 0x4
662 0x0 0x0 0x0 0x2 &gic 0x0 0xc9 0x4
663 0x0 0x0 0x0 0x3 &gic 0x0 0xca 0x4
664 0x0 0x0 0x0 0x4 &gic 0x0 0xcb 0x4>;
666 clocks = <&pcie1clk 0>;
677 reg = < 0x00 0x1f2d0000 0x0 0x00010000 /* Controller registers */
678 0x90 0xd0000000 0x0 0x00040000>; /* PCI config space */
680 ranges = <0x01000000 0x00 0x00000000 0x90 0x10000000 0x00 0x00010000 /* io */
681 0x02000000 0x00 0x80000000 0x91 0x80000000 0x00 0x80000000 /* mem */
682 0x43000000 0x94 0x00000000 0x94 0x00000000 0x04 0x00000000>; /* mem */
683 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
684 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
685 bus-range = <0x00 0xff>;
686 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
687 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xce 0x4
688 0x0 0x0 0x0 0x2 &gic 0x0 0xcf 0x4
689 0x0 0x0 0x0 0x3 &gic 0x0 0xd0 0x4
690 0x0 0x0 0x0 0x4 &gic 0x0 0xd1 0x4>;
692 clocks = <&pcie2clk 0>;
703 reg = < 0x00 0x1f500000 0x0 0x00010000 /* Controller registers */
704 0xa0 0xd0000000 0x0 0x00040000>; /* PCI config space */
706 ranges = <0x01000000 0x00 0x00000000 0xa0 0x10000000 0x00 0x00010000 /* io */
707 0x02000000 0x00 0x80000000 0xa1 0x80000000 0x00 0x80000000 /* mem */
708 0x43000000 0xb0 0x00000000 0xb0 0x00000000 0x10 0x00000000>; /* mem */
709 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
710 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
711 bus-range = <0x00 0xff>;
712 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
713 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xd4 0x4
714 0x0 0x0 0x0 0x2 &gic 0x0 0xd5 0x4
715 0x0 0x0 0x0 0x3 &gic 0x0 0xd6 0x4
716 0x0 0x0 0x0 0x4 &gic 0x0 0xd7 0x4>;
718 clocks = <&pcie3clk 0>;
729 reg = < 0x00 0x1f510000 0x0 0x00010000 /* Controller registers */
730 0xc0 0xd0000000 0x0 0x00200000>; /* PCI config space */
732 ranges = <0x01000000 0x00 0x00000000 0xc0 0x10000000 0x00 0x00010000 /* io */
733 0x02000000 0x00 0x80000000 0xc1 0x80000000 0x00 0x80000000 /* mem */
734 0x43000000 0xc8 0x00000000 0xc8 0x00000000 0x08 0x00000000>; /* mem */
735 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
736 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
737 bus-range = <0x00 0xff>;
738 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
739 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xda 0x4
740 0x0 0x0 0x0 0x2 &gic 0x0 0xdb 0x4
741 0x0 0x0 0x0 0x3 &gic 0x0 0xdc 0x4
742 0x0 0x0 0x0 0x4 &gic 0x0 0xdd 0x4>;
744 clocks = <&pcie4clk 0>;
750 reg = <0x0 0x10540000 0x0 0xa000>;
752 interrupts = <0x0 0x0 0x4>,
753 <0x0 0x1 0x4>,
754 <0x0 0x2 0x4>,
755 <0x0 0x3 0x4>,
756 <0x0 0x4 0x4>,
757 <0x0 0x5 0x4>,
758 <0x0 0x6 0x4>,
759 <0x0 0x7 0x4>;
764 mboxes = <&mailbox 0>;
775 reg = <0 0x1c020000 0x0 0x1000>;
779 interrupts = <0x0 0x4c 0x4>;
785 reg = <0 0x1c021000 0x0 0x1000>;
789 interrupts = <0x0 0x4d 0x4>;
795 reg = <0 0x1c022000 0x0 0x1000>;
799 interrupts = <0x0 0x4e 0x4>;
805 reg = <0 0x1c023000 0x0 0x1000>;
809 interrupts = <0x0 0x4f 0x4>;
814 reg = <0x0 0x1c000000 0x0 0x100>;
815 interrupts = <0x0 0x49 0x4>;
819 clocks = <&sdioclk 0>, <&ahbclk 0>;
824 reg = <0x0 0x1701c000 0x0 0x40>;
831 reg = <0x0 0x1c024000 0x0 0x1000>;
833 #size-cells = <0>;
835 porta: gpio-controller@0 {
840 reg = <0>;
847 #size-cells = <0>;
849 reg = <0x0 0x10512000 0x0 0x1000>;
850 interrupts = <0 0x44 0x4>;
852 clocks = <&ahbclk 0>;
853 bus_num = <0>;
858 reg = <0x0 0x1f21a000 0x0 0x100>;
860 clocks = <&sataphy1clk 0>;
868 reg = <0x0 0x1f22a000 0x0 0x100>;
870 clocks = <&sataphy2clk 0>;
878 reg = <0x0 0x1f23a000 0x0 0x100>;
880 clocks = <&sataphy3clk 0>;
888 reg = <0x0 0x1a000000 0x0 0x1000>,
889 <0x0 0x1f210000 0x0 0x1000>,
890 <0x0 0x1f21d000 0x0 0x1000>,
891 <0x0 0x1f21e000 0x0 0x1000>,
892 <0x0 0x1f217000 0x0 0x1000>;
893 interrupts = <0x0 0x86 0x4>;
896 clocks = <&sata01clk 0>;
897 phys = <&phy1 0>;
903 reg = <0x0 0x1a400000 0x0 0x1000>,
904 <0x0 0x1f220000 0x0 0x1000>,
905 <0x0 0x1f22d000 0x0 0x1000>,
906 <0x0 0x1f22e000 0x0 0x1000>,
907 <0x0 0x1f227000 0x0 0x1000>;
908 interrupts = <0x0 0x87 0x4>;
911 clocks = <&sata23clk 0>;
912 phys = <&phy2 0>;
918 reg = <0x0 0x1a800000 0x0 0x1000>,
919 <0x0 0x1f230000 0x0 0x1000>,
920 <0x0 0x1f23d000 0x0 0x1000>,
921 <0x0 0x1f23e000 0x0 0x1000>;
922 interrupts = <0x0 0x88 0x4>;
925 clocks = <&sata45clk 0>;
926 phys = <&phy3 0>;
934 reg = <0x0 0x19000000 0x0 0x100000>;
935 interrupts = <0x0 0x89 0x4>;
943 reg = <0x0 0x19800000 0x0 0x100000>;
944 interrupts = <0x0 0x8a 0x4>;
951 reg = <0x0 0x17001000 0x0 0x400>;
954 interrupts = <0x0 0x28 0x1>,
955 <0x0 0x29 0x1>,
956 <0x0 0x2a 0x1>,
957 <0x0 0x2b 0x1>,
958 <0x0 0x2c 0x1>,
959 <0x0 0x2d 0x1>;
967 reg = <0x0 0x10510000 0x0 0x400>;
968 interrupts = <0x0 0x46 0x4>;
970 clocks = <&rtcclk 0>;
976 #size-cells = <0>;
977 reg = <0x0 0x17020000 0x0 0xd100>;
978 clocks = <&menetclk 0>;
984 reg = <0x0 0x17020000 0x0 0xd100>,
985 <0x0 0x17030000 0x0 0xc300>,
986 <0x0 0x10000000 0x0 0x200>;
988 interrupts = <0x0 0x3c 0x4>;
990 clocks = <&menetclk 0>;
998 #size-cells = <0>;
1001 reg = <0x3>;
1010 reg = <0x0 0x1f210000 0x0 0xd100>,
1011 <0x0 0x1f200000 0x0 0xc300>,
1012 <0x0 0x1b000000 0x0 0x200>;
1014 interrupts = <0x0 0xa0 0x4>,
1015 <0x0 0xa1 0x4>;
1017 clocks = <&sge0clk 0>;
1026 reg = <0x0 0x1f210030 0x0 0xd100>,
1027 <0x0 0x1f200000 0x0 0xc300>,
1028 <0x0 0x1b000000 0x0 0x8000>;
1030 interrupts = <0x0 0xac 0x4>,
1031 <0x0 0xad 0x4>;
1042 reg = <0x0 0x1f610000 0x0 0xd100>,
1043 <0x0 0x1f600000 0x0 0xc300>,
1044 <0x0 0x18000000 0x0 0x200>;
1046 interrupts = <0x0 0x60 0x4>,
1047 <0x0 0x61 0x4>,
1048 <0x0 0x62 0x4>,
1049 <0x0 0x63 0x4>,
1050 <0x0 0x64 0x4>,
1051 <0x0 0x65 0x4>,
1052 <0x0 0x66 0x4>,
1053 <0x0 0x67 0x4>;
1054 channel = <0>;
1056 clocks = <&xge0clk 0>;
1065 reg = <0x0 0x1f620000 0x0 0xd100>,
1066 <0x0 0x1f600000 0x0 0xc300>,
1067 <0x0 0x18000000 0x0 0x8000>;
1069 interrupts = <0x0 0x6c 0x4>,
1070 <0x0 0x6d 0x4>;
1073 clocks = <&xge1clk 0>;
1081 reg = <0x0 0x10520000 0x0 0x100>;
1082 interrupts = <0x0 0x41 0x4>;
1083 clocks = <&rngpkaclk 0>;
1089 reg = <0x0 0x1f270000 0x0 0x10000>,
1090 <0x0 0x1f200000 0x0 0x10000>,
1091 <0x0 0x1b000000 0x0 0x400000>,
1092 <0x0 0x1054a000 0x0 0x100>;
1093 interrupts = <0x0 0x82 0x4>,
1094 <0x0 0xb8 0x4>,
1095 <0x0 0xb9 0x4>,
1096 <0x0 0xba 0x4>,
1097 <0x0 0xbb 0x4>;
1099 clocks = <&dmaclk 0>;