Lines Matching +full:phy +full:- +full:sata3
1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * dts file for AppliedMicro (APM) X-Gene Shadowcat SOC
9 compatible = "apm,xgene-shadowcat";
10 interrupt-parent = <&gic>;
11 #address-cells = <2>;
12 #size-cells = <2>;
15 #address-cells = <2>;
16 #size-cells = <0>;
22 enable-method = "spin-table";
23 cpu-release-addr = <0x1 0x0000fff8>;
24 next-level-cache = <&xgene_L2_0>;
25 #clock-cells = <1>;
32 enable-method = "spin-table";
33 cpu-release-addr = <0x1 0x0000fff8>;
34 next-level-cache = <&xgene_L2_0>;
35 #clock-cells = <1>;
42 enable-method = "spin-table";
43 cpu-release-addr = <0x1 0x0000fff8>;
44 next-level-cache = <&xgene_L2_1>;
45 #clock-cells = <1>;
52 enable-method = "spin-table";
53 cpu-release-addr = <0x1 0x0000fff8>;
54 next-level-cache = <&xgene_L2_1>;
55 #clock-cells = <1>;
62 enable-method = "spin-table";
63 cpu-release-addr = <0x1 0x0000fff8>;
64 next-level-cache = <&xgene_L2_2>;
65 #clock-cells = <1>;
72 enable-method = "spin-table";
73 cpu-release-addr = <0x1 0x0000fff8>;
74 next-level-cache = <&xgene_L2_2>;
75 #clock-cells = <1>;
82 enable-method = "spin-table";
83 cpu-release-addr = <0x1 0x0000fff8>;
84 next-level-cache = <&xgene_L2_3>;
85 #clock-cells = <1>;
92 enable-method = "spin-table";
93 cpu-release-addr = <0x1 0x0000fff8>;
94 next-level-cache = <&xgene_L2_3>;
95 #clock-cells = <1>;
98 xgene_L2_0: l2-cache-0 {
100 cache-level = <2>;
101 cache-unified;
103 xgene_L2_1: l2-cache-1 {
105 cache-level = <2>;
106 cache-unified;
108 xgene_L2_2: l2-cache-2 {
110 cache-level = <2>;
111 cache-unified;
113 xgene_L2_3: l2-cache-3 {
115 cache-level = <2>;
116 cache-unified;
120 gic: interrupt-controller@78090000 {
121 compatible = "arm,cortex-a15-gic";
122 #interrupt-cells = <3>;
123 #address-cells = <2>;
124 #size-cells = <2>;
125 interrupt-controller;
133 compatible = "arm,gic-v2m-frame";
134 msi-controller;
138 compatible = "arm,gic-v2m-frame";
139 msi-controller;
143 compatible = "arm,gic-v2m-frame";
144 msi-controller;
148 compatible = "arm,gic-v2m-frame";
149 msi-controller;
153 compatible = "arm,gic-v2m-frame";
154 msi-controller;
158 compatible = "arm,gic-v2m-frame";
159 msi-controller;
163 compatible = "arm,gic-v2m-frame";
164 msi-controller;
168 compatible = "arm,gic-v2m-frame";
169 msi-controller;
173 compatible = "arm,gic-v2m-frame";
174 msi-controller;
178 compatible = "arm,gic-v2m-frame";
179 msi-controller;
183 compatible = "arm,gic-v2m-frame";
184 msi-controller;
188 compatible = "arm,gic-v2m-frame";
189 msi-controller;
193 compatible = "arm,gic-v2m-frame";
194 msi-controller;
198 compatible = "arm,gic-v2m-frame";
199 msi-controller;
203 compatible = "arm,gic-v2m-frame";
204 msi-controller;
208 compatible = "arm,gic-v2m-frame";
209 msi-controller;
215 compatible = "arm,armv8-pmuv3";
220 compatible = "arm,armv8-timer";
222 <1 13 0xff08>, /* Non-secure Phys IRQ */
225 clock-frequency = <50000000>;
229 compatible = "simple-bus";
230 #address-cells = <2>;
231 #size-cells = <2>;
235 #address-cells = <2>;
236 #size-cells = <2>;
240 compatible = "fixed-clock";
241 #clock-cells = <1>;
242 clock-frequency = <100000000>;
243 clock-output-names = "refclk";
247 compatible = "apm,xgene-pcppll-v2-clock";
248 #clock-cells = <1>;
251 clock-output-names = "pmdpll";
255 compatible = "apm,xgene-pmd-clock";
256 #clock-cells = <1>;
259 clock-output-names = "pmd0clk";
263 compatible = "apm,xgene-pmd-clock";
264 #clock-cells = <1>;
267 clock-output-names = "pmd1clk";
271 compatible = "apm,xgene-pmd-clock";
272 #clock-cells = <1>;
275 clock-output-names = "pmd2clk";
279 compatible = "apm,xgene-pmd-clock";
280 #clock-cells = <1>;
283 clock-output-names = "pmd3clk";
287 compatible = "apm,xgene-socpll-v2-clock";
288 #clock-cells = <1>;
291 clock-output-names = "socpll";
295 compatible = "fixed-factor-clock";
296 #clock-cells = <1>;
298 clock-mult = <1>;
299 clock-div = <2>;
300 clock-output-names = "socplldiv2";
304 compatible = "apm,xgene-device-clock";
305 #clock-cells = <1>;
308 reg-names = "div-reg";
309 divider-offset = <0x164>;
310 divider-width = <0x5>;
311 divider-shift = <0x0>;
312 clock-output-names = "ahbclk";
316 compatible = "apm,xgene-device-clock";
317 #clock-cells = <1>;
320 reg-names = "div-reg";
321 divider-offset = <0x10>;
322 divider-width = <0x2>;
323 divider-shift = <0x0>;
324 clock-output-names = "sbapbclk";
328 compatible = "apm,xgene-device-clock";
329 #clock-cells = <1>;
333 reg-names = "csr-reg", "div-reg";
334 csr-offset = <0x0>;
335 csr-mask = <0x2>;
336 enable-offset = <0x8>;
337 enable-mask = <0x2>;
338 divider-offset = <0x178>;
339 divider-width = <0x8>;
340 divider-shift = <0x0>;
341 clock-output-names = "sdioclk";
345 compatible = "apm,xgene-device-clock";
346 #clock-cells = <1>;
349 reg-names = "csr-reg";
350 clock-output-names = "pcie0clk";
354 compatible = "apm,xgene-device-clock";
355 #clock-cells = <1>;
358 reg-names = "csr-reg";
359 clock-output-names = "pcie1clk";
363 compatible = "apm,xgene-device-clock";
364 #clock-cells = <1>;
367 reg-names = "csr-reg";
368 enable-mask = <0x3>;
369 csr-mask = <0x3>;
370 clock-output-names = "xge0clk";
374 compatible = "apm,xgene-device-clock";
375 #clock-cells = <1>;
378 reg-names = "csr-reg";
379 enable-mask = <0x3>;
380 csr-mask = <0x3>;
381 clock-output-names = "xge1clk";
385 compatible = "apm,xgene-device-clock";
386 #clock-cells = <1>;
389 reg-names = "csr-reg";
390 csr-offset = <0xc>;
391 csr-mask = <0x10>;
392 enable-offset = <0x10>;
393 enable-mask = <0x10>;
394 clock-output-names = "rngpkaclk";
398 compatible = "apm,xgene-device-clock";
399 #clock-cells = <1>;
402 reg-names = "csr-reg";
403 csr-offset = <0x0>;
404 csr-mask = <0x40>;
405 enable-offset = <0x8>;
406 enable-mask = <0x40>;
407 clock-output-names = "i2c4clk";
411 scu: system-clk-controller@17000000 {
412 compatible = "apm,xgene-scu","syscon";
417 compatible = "syscon-reboot";
424 compatible = "apm,xgene-csw", "syscon";
429 compatible = "apm,xgene-mcb", "syscon";
434 compatible = "apm,xgene-mcb", "syscon";
439 compatible = "apm,xgene-efuse", "syscon";
444 compatible = "apm,xgene-edac";
445 #address-cells = <2>;
446 #size-cells = <2>;
448 regmap-csw = <&csw>;
449 regmap-mcba = <&mcba>;
450 regmap-mcbb = <&mcbb>;
451 regmap-efuse = <&efuse>;
458 compatible = "apm,xgene-edac-mc";
460 memory-controller = <0>;
464 compatible = "apm,xgene-edac-mc";
466 memory-controller = <1>;
470 compatible = "apm,xgene-edac-mc";
472 memory-controller = <2>;
476 compatible = "apm,xgene-edac-mc";
478 memory-controller = <3>;
482 compatible = "apm,xgene-edac-pmd";
484 pmd-controller = <0>;
488 compatible = "apm,xgene-edac-pmd";
490 pmd-controller = <1>;
494 compatible = "apm,xgene-edac-pmd";
496 pmd-controller = <2>;
500 compatible = "apm,xgene-edac-pmd";
502 pmd-controller = <3>;
506 compatible = "apm,xgene-edac-l3-v2";
511 compatible = "apm,xgene-edac-soc";
517 compatible = "apm,xgene-pmu-v2";
518 #address-cells = <2>;
519 #size-cells = <2>;
521 regmap-csw = <&csw>;
522 regmap-mcba = <&mcba>;
523 regmap-mcbb = <&mcbb>;
528 compatible = "apm,xgene-pmu-l3c";
533 compatible = "apm,xgene-pmu-iob";
538 compatible = "apm,xgene-pmu-mcb";
540 enable-bit-index = <0>;
544 compatible = "apm,xgene-pmu-mcb";
546 enable-bit-index = <1>;
550 compatible = "apm,xgene-pmu-mc";
552 enable-bit-index = <0>;
556 compatible = "apm,xgene-pmu-mc";
558 enable-bit-index = <1>;
562 compatible = "apm,xgene-pmu-mc";
564 enable-bit-index = <2>;
568 compatible = "apm,xgene-pmu-mc";
570 enable-bit-index = <3>;
575 compatible = "apm,xgene-slimpro-mbox";
577 #mbox-cells = <1>;
589 compatible = "apm,xgene-slimpro-i2c";
594 compatible = "apm,xgene-slimpro-hwmon";
601 reg-shift = <2>;
602 clock-frequency = <10000000>;
603 interrupt-parent = <&gic>;
607 /* Node-name might need to be coded as dwusb for backward compatibility */
613 dma-coherent;
620 compatible = "apm,xgene-pcie", "apm,xgene2-pcie";
621 #interrupt-cells = <1>;
622 #size-cells = <2>;
623 #address-cells = <3>;
626 reg-names = "csr", "cfg";
630 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
632 bus-range = <0x00 0xff>;
633 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
634 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 0x10 0x4
638 dma-coherent;
640 msi-parent = <&v2m0>;
646 compatible = "apm,xgene-pcie", "apm,xgene2-pcie";
647 #interrupt-cells = <1>;
648 #size-cells = <2>;
649 #address-cells = <3>;
652 reg-names = "csr", "cfg";
656 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
658 bus-range = <0x00 0xff>;
659 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
660 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 0x16 0x4
664 dma-coherent;
666 msi-parent = <&v2m0>;
670 compatible = "apm,xgene-ahci-v2";
676 dma-coherent;
680 compatible = "apm,xgene-ahci-v2";
686 dma-coherent;
689 sata3: sata@1a400000 {
690 compatible = "apm,xgene-ahci-v2";
696 dma-coherent;
700 compatible = "arasan,sdhci-4.9a";
703 dma-coherent;
704 no-1-8-v;
705 clock-names = "clk_xin", "clk_ahb";
710 compatible = "apm,xgene-gpio";
712 gpio-controller;
713 #gpio-cells = <2>;
717 compatible = "snps,dw-apb-gpio";
719 #address-cells = <1>;
720 #size-cells = <0>;
722 porta: gpio-controller@0 {
723 compatible = "snps,dw-apb-gpio-port";
724 gpio-controller;
725 #gpio-cells = <2>;
726 snps,nr-gpios = <32>;
732 compatible = "apm,xgene-gpio-sb";
734 #gpio-cells = <2>;
735 gpio-controller;
744 interrupt-parent = <&gic>;
745 #interrupt-cells = <2>;
746 interrupt-controller;
747 apm,nr-gpios = <22>;
748 apm,nr-irqs = <8>;
749 apm,irq-start = <8>;
753 compatible = "apm,xgene-mdio-xfi";
754 #address-cells = <1>;
755 #size-cells = <0>;
761 compatible = "apm,xgene2-sgenet";
768 dma-coherent;
770 local-mac-address = [00 01 73 00 00 01];
771 phy-connection-type = "sgmii";
772 phy-handle = <&sgenet0phy>;
776 compatible = "apm,xgene2-xgenet";
790 port-id = <1>;
791 dma-coherent;
793 local-mac-address = [00 01 73 00 00 02];
794 phy-connection-type = "xgmii";
798 compatible = "apm,xgene-rng";
805 #address-cells = <1>;
806 #size-cells = <0>;
807 compatible = "snps,designware-i2c";
810 #clock-cells = <1>;
816 #address-cells = <1>;
817 #size-cells = <0>;
818 compatible = "snps,designware-i2c";