Lines Matching full:clkc

8 #include <dt-bindings/clock/g12a-clkc.h>
36 			clocks = <&clkc CLKID_HDMI>,
37 				 <&clkc CLKID_HTX_PCLK>,
38 				 <&clkc CLKID_VPU_INTR>;
46 			clocks = <&clkc CLKID_HDMI>,
47 				 <&clkc CLKID_HTX_PCLK>,
48 				 <&clkc CLKID_VPU_INTR>;
55 		clocks = <&clkc CLKID_EFUSE>;
153 			clocks = <&clkc CLKID_PCIE_PHY
154 				  &clkc CLKID_PCIE_COMB
155 				  &clkc CLKID_PCIE_PLL>;
177 			clocks = <&clkc CLKID_ETH>,
178 				 <&clkc CLKID_FCLK_DIV2>,
179 				 <&clkc CLKID_MPLL2>,
180 				 <&clkc CLKID_FCLK_DIV2>;
209 				clocks = <&clkc CLKID_HDMI>,
210 					 <&clkc CLKID_HTX_PCLK>,
211 					 <&clkc CLKID_VPU_INTR>;
243 					clocks = <&clkc CLKID_RNG0>;
253 				clocks = <&clkc CLKID_AUDIO_CODEC>;
1548 				clocks = <&clkc CLKID_TS>;
1558 				clocks = <&clkc CLKID_TS>;
1613 					clkc: clock-controller {
1614 						compatible = "amlogic,g12a-clkc";
1638 						clocks = <&clkc CLKID_VPU>,
1639 							 <&clkc CLKID_VAPB>;
1647 						assigned-clocks = <&clkc CLKID_VPU_0_SEL>,
1648 								  <&clkc CLKID_VPU_0>,
1649 								  <&clkc CLKID_VPU>, /* Glitch free mux */
1650 								  <&clkc CLKID_VAPB_0_SEL>,
1651 								  <&clkc CLKID_VAPB_0>,
1652 								  <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */
1653 						assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
1655 									 <&clkc CLKID_VPU_0>,
1656 									 <&clkc CLKID_FCLK_DIV4>,
1658 									 <&clkc CLKID_VAPB_0>;
1672 				clocks = <&clkc CLKID_PCIE_PLL>;
1676 				assigned-clocks = <&clkc CLKID_PCIE_PLL>;
1684 				clocks = <&clkc CLKID_ETH_PHY>,
1686 					 <&clkc CLKID_MPLL_50M>;
1733 					clocks = <&xtal>, <&clkc CLKID_CLK81>;
2077 				clocks = <&clkc CLKID_I2C>;
2121 			clocks = <&clkc CLKID_PARSER>,
2122 				 <&clkc CLKID_DOS>,
2123 				 <&clkc CLKID_VDEC_1>,
2124 				 <&clkc CLKID_VDEC_HEVC>,
2125 				 <&clkc CLKID_VDEC_HEVCF>;
2202 				clocks = <&clkc CLKID_SPICC0>,
2203 					 <&clkc CLKID_SPICC0_SCLK>;
2214 				clocks = <&clkc CLKID_SPICC1>,
2215 					 <&clkc CLKID_SPICC1_SCLK>;
2228 				clocks = <&clkc CLKID_CLK81>;
2259 				clocks = <&clkc CLKID_I2C>;
2269 				clocks = <&clkc CLKID_I2C>;
2279 				clocks = <&clkc CLKID_I2C>;
2289 				clocks = <&clkc CLKID_I2C>;
2302 				clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>;
2312 				clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
2322 				clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
2334 			clocks = <&clkc CLKID_SD_EMMC_A>,
2335 				 <&clkc CLKID_SD_EMMC_A_CLK0>,
2336 				 <&clkc CLKID_FCLK_DIV2>;
2346 			clocks = <&clkc CLKID_SD_EMMC_B>,
2347 				 <&clkc CLKID_SD_EMMC_B_CLK0>,
2348 				 <&clkc CLKID_FCLK_DIV2>;
2358 			clocks = <&clkc CLKID_SD_EMMC_C>,
2359 				 <&clkc CLKID_SD_EMMC_C_CLK0>,
2360 				 <&clkc CLKID_FCLK_DIV2>;
2374 			clocks = <&clkc CLKID_USB>;
2387 				clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
2416 			clocks = <&clkc CLKID_MALI>;
2502 		clocks = <&clkc CLKID_NNA_CORE_CLK>,
2503 			 <&clkc CLKID_NNA_AXI_CLK>;