Lines Matching +full:0 +full:x2184
12 cpu@0 {
19 reg = <0x80000000 0x40000000>; /* 1 GB */
47 pinctrl-0 = <&debug_leds>;
54 #clock-cells = <0>;
62 OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT | MUX_MODE4) /* mcspi2_somi.gpio_180 -> LIS302 INT1 */
63 OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT | MUX_MODE4) /* mcspi2_cs0.gpio_181 -> LIS302 INT2 */
69 OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE4) /* dss_data22.gpio_92 */
75 OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk */
76 OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd */
77 OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0 */
78 OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1 */
79 OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2 */
80 OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3 */
86 OMAP3_CORE1_IOPAD(0x207c, PIN_OUTPUT | MUX_MODE4) /* gpio 35 - wlan enable */
87 OMAP3_CORE1_IOPAD(0x208a, PIN_INPUT | MUX_MODE4) /* gpio 42 - wlan irq */
93 OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE1) /* ssi1_dat_tx */
94 OMAP3_CORE1_IOPAD(0x217e, PIN_OUTPUT | MUX_MODE1) /* ssi1_flag_tx */
95 OMAP3_CORE1_IOPAD(0x2180, PIN_INPUT_PULLUP | MUX_MODE1) /* ssi1_rdy_tx */
96 OMAP3_CORE1_IOPAD(0x2182, PIN_INPUT | MUX_MODE4) /* ssi1_wake_tx (cawake) */
97 OMAP3_CORE1_IOPAD(0x2184, PIN_INPUT | MUX_MODE1) /* ssi1_dat_rx */
98 OMAP3_CORE1_IOPAD(0x2186, PIN_INPUT | MUX_MODE1) /* ssi1_flag_rx */
99 OMAP3_CORE1_IOPAD(0x2188, PIN_OUTPUT | MUX_MODE1) /* ssi1_rdy_rx */
100 OMAP3_CORE1_IOPAD(0x218a, PIN_OUTPUT | MUX_MODE1) /* ssi1_wake */
106 OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE7) /* ssi1_dat_tx */
107 OMAP3_CORE1_IOPAD(0x217e, PIN_OUTPUT | MUX_MODE7) /* ssi1_flag_tx */
108 OMAP3_CORE1_IOPAD(0x2180, PIN_INPUT_PULLDOWN | MUX_MODE7) /* ssi1_rdy_tx */
109 OMAP3_CORE1_IOPAD(0x2182, PIN_INPUT | MUX_MODE4) /* ssi1_wake_tx (cawake) */
110 OMAP3_CORE1_IOPAD(0x2184, PIN_INPUT | MUX_MODE7) /* ssi1_dat_rx */
111 OMAP3_CORE1_IOPAD(0x2186, PIN_INPUT | MUX_MODE7) /* ssi1_flag_rx */
112 OMAP3_CORE1_IOPAD(0x2188, PIN_OUTPUT | MUX_MODE4) /* ssi1_rdy_rx */
113 OMAP3_CORE1_IOPAD(0x218a, PIN_OUTPUT | MUX_MODE7) /* ssi1_wake */
119 OMAP3_CORE1_IOPAD(0x207a, PIN_INPUT | MUX_MODE4) /* gpio_34 (ape_rst_rq) */
120 OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE4) /* gpio_88 (cmt_rst_rq) */
121 OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE4) /* gpio_93 (cmt_apeslpx) */
127 OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT_PULLUP | MUX_MODE0) /* uart2_cts */
128 OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT | MUX_MODE0) /* uart2_rts */
129 OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0) /* uart2_tx */
130 OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0) /* uart2_rx */
138 OMAP3630_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4) /* gpio_23 (cmt_en) */
147 reg = <0x48>;
165 ti,pullups = <0x000001>; /* BIT(0) */
166 ti,pulldowns = <0x008106>; /* BIT(1) | BIT(2) | BIT(8) | BIT(15) */
260 #size-cells = <0>;
261 reg = <0x30>;
263 as3645a_flash: flash@0 {
264 reg = <0x0>;
271 reg = <0x1>;
282 reg = <0x1d>;
288 pinctrl-0 = <&accelerator_pins>;
334 pinctrl-0 = <&mmc2_pins>;
350 interface-type = <0>;
359 ranges = <0 0 0x04000000 0x1000000>; /* CS0: 16MB for OneNAND */
361 onenand@0,0 {
365 reg = <0 0 0x20000>; /* CS0, offset 0, IO size 128K */
373 * cs0 GPMC_CS_CONFIG1: 0xfd001202
374 * cs0 GPMC_CS_CONFIG2: 0x00181800
375 * cs0 GPMC_CS_CONFIG3: 0x00030300
376 * cs0 GPMC_CS_CONFIG4: 0x18001804
377 * cs0 GPMC_CS_CONFIG5: 0x03171d1d
378 * cs0 GPMC_CS_CONFIG6: 0x97080000
388 gpmc,cs-on-ns = <0>;
391 gpmc,adv-on-ns = <0>;
396 gpmc,we-on-ns = <0>;
402 gpmc,bus-turnaround-ns = <0>;
403 gpmc,cycle2cycle-delay-ns = <0>;
404 gpmc,wait-monitoring-ns = <0>;
415 partition@0 {
417 reg = <0x00000000 0x00100000>;
421 reg = <0x00100000 0x002c0000>;
425 reg = <0x003c0000 0x01000000>;
429 reg = <0x013c0000 0x00200000>;
433 reg = <0x015c0000 0x1ca40000>;
437 reg = <0x1e000000 0x02000000>;
441 reg = <0x00000000 0x20000000>;
448 pinctrl-0 = <&ssi_pins>;
455 pinctrl-0 = <&modem_pins1 &modem_pins2>;
457 hsi-channel-ids = <0>, <1>, <2>, <3>;
484 pinctrl-0 = <&uart2_pins>;