Lines Matching +full:0 +full:x2184
46 cpu@0 {
58 pinctrl-0 = <&debug_leds>;
64 reg = <0x80000000 0x10000000>; /* 256 MB */
117 gpios = <&gpio6 0 GPIO_ACTIVE_LOW>; /* 160 */
156 io-channels = <&twl_madc 0>, <&twl_madc 4>, <&twl_madc 12>;
164 ti,clock-source = <0x00>; /* timer_sys_ck */
169 pwms = <&pwm9 0 26316 0>; /* 38000 Hz */
181 #clock-cells = <0>;
190 pinctrl-0 = <&camera_pins>;
200 data-lanes = <0>;
201 lane-polarity = <0 0>;
202 /* Select strobe = <1> for back camera, <0> for front camera */
214 OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT_PULLUP | MUX_MODE0) /* uart2_cts */
215 OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT | MUX_MODE0) /* uart2_rts */
216 OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0) /* uart2_tx */
217 OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0) /* uart2_rx */
223 OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0) /* uart3_rx */
224 OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx */
230 OMAP3_CORE1_IOPAD(0x20b4, PIN_INPUT_PULLDOWN | MUX_MODE4) /* gpmc_ncs3.gpio_54 */
231 OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE4) /* dss_data16.gpio_86 */
232 OMAP3_CORE1_IOPAD(0x219c, PIN_OUTPUT | MUX_MODE4) /* uart3_rts_sd.gpio_164 */
240 OMAP3_CORE1_IOPAD(0x207a, PIN_OUTPUT | MUX_MODE0) /* gpmc_a1.gpmc_a1 */
241 OMAP3_CORE1_IOPAD(0x207c, PIN_OUTPUT | MUX_MODE0) /* gpmc_a2.gpmc_a2 */
242 OMAP3_CORE1_IOPAD(0x207e, PIN_OUTPUT | MUX_MODE0) /* gpmc_a3.gpmc_a3 */
245 OMAP3_CORE1_IOPAD(0x209e, PIN_INPUT | MUX_MODE0) /* gpmc_d8.gpmc_d8 */
246 OMAP3_CORE1_IOPAD(0x20a0, PIN_INPUT | MUX_MODE0) /* gpmc_d9.gpmc_d9 */
247 OMAP3_CORE1_IOPAD(0x20a2, PIN_INPUT | MUX_MODE0) /* gpmc_d10.gpmc_d10 */
248 OMAP3_CORE1_IOPAD(0x20a4, PIN_INPUT | MUX_MODE0) /* gpmc_d11.gpmc_d11 */
249 OMAP3_CORE1_IOPAD(0x20a6, PIN_INPUT | MUX_MODE0) /* gpmc_d12.gpmc_d12 */
250 OMAP3_CORE1_IOPAD(0x20a8, PIN_INPUT | MUX_MODE0) /* gpmc_d13.gpmc_d13 */
251 OMAP3_CORE1_IOPAD(0x20aa, PIN_INPUT | MUX_MODE0) /* gpmc_d14.gpmc_d14 */
252 OMAP3_CORE1_IOPAD(0x20ac, PIN_INPUT | MUX_MODE0) /* gpmc_d15.gpmc_d15 */
258 OMAP3_CORE1_IOPAD(0x20b0, PIN_OUTPUT | MUX_MODE0) /* gpmc_ncs1.gpmc_ncs1 */
259 OMAP3_CORE1_IOPAD(0x20be, PIN_INPUT | MUX_MODE0) /* gpmc_clk.gpmc_clk */
265 OMAP3_CORE1_IOPAD(0x21ba, PIN_INPUT | MUX_MODE0) /* i2c1_scl */
266 OMAP3_CORE1_IOPAD(0x21bc, PIN_INPUT | MUX_MODE0) /* i2c1_sda */
272 OMAP3_CORE1_IOPAD(0x21be, PIN_INPUT | MUX_MODE0) /* i2c2_scl */
273 OMAP3_CORE1_IOPAD(0x21c0, PIN_INPUT | MUX_MODE0) /* i2c2_sda */
279 OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT | MUX_MODE0) /* i2c3_scl */
280 OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT | MUX_MODE0) /* i2c3_sda */
286 OMAP3_CORE1_IOPAD(0x2198, PIN_OUTPUT | MUX_MODE4) /* mcbsp1_clkx.gpio_162 */
292 OMAP3_CORE1_IOPAD(0x218c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mcspi4_clk */
293 OMAP3_CORE1_IOPAD(0x2192, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mcspi4_somi */
294 OMAP3_CORE1_IOPAD(0x2190, PIN_OUTPUT | MUX_MODE1) /* mcspi4_simo */
295 OMAP3_CORE1_IOPAD(0x2196, PIN_OUTPUT | MUX_MODE1) /* mcspi4_cs0 */
301 OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk */
302 OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd */
303 OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0 */
304 OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1 */
305 OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2 */
306 OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3 */
312 OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk */
313 OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd */
314 OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0 */
315 OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1 */
316 OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2 */
317 OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3 */
318 OMAP3_CORE1_IOPAD(0x2164, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat4 */
319 OMAP3_CORE1_IOPAD(0x2166, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat5 */
320 OMAP3_CORE1_IOPAD(0x2168, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat6 */
321 OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat7 */
327 OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE4) /* RX51_LCD_RESET_GPIO */
333 OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE1) /* dss_data10.sdi_dat1n */
334 OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE1) /* dss_data11.sdi_dat1p */
335 OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE1) /* dss_data12.sdi_dat2n */
336 OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE1) /* dss_data13.sdi_dat2p */
338 OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE1) /* dss_data22.sdi_clkp */
339 OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE1) /* dss_data23.sdi_clkn */
345 OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE4) /* gpio 87 => wl1251 enable */
346 OMAP3_CORE1_IOPAD(0x208a, PIN_INPUT | MUX_MODE4) /* gpio 42 => wl1251 irq */
352 OMAP3_CORE1_IOPAD(0x2180, PIN_INPUT_PULLUP | MUX_MODE1) /* ssi1_rdy_tx */
353 OMAP3_CORE1_IOPAD(0x217e, PIN_OUTPUT | MUX_MODE1) /* ssi1_flag_tx */
354 OMAP3_CORE1_IOPAD(0x2182, PIN_INPUT | MUX_MODE4) /* ssi1_wake_tx (cawake) */
355 OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE1) /* ssi1_dat_tx */
356 OMAP3_CORE1_IOPAD(0x2184, PIN_INPUT | MUX_MODE1) /* ssi1_dat_rx */
357 OMAP3_CORE1_IOPAD(0x2186, PIN_INPUT | MUX_MODE1) /* ssi1_flag_rx */
358 OMAP3_CORE1_IOPAD(0x2188, PIN_OUTPUT | MUX_MODE1) /* ssi1_rdy_rx */
359 OMAP3_CORE1_IOPAD(0x218a, PIN_OUTPUT | MUX_MODE1) /* ssi1_wake */
365 OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE4) /* gpio 70 => cmt_apeslpx */
366 OMAP3_CORE1_IOPAD(0x20e0, PIN_INPUT | MUX_MODE4) /* gpio 72 => ape_rst_rq */
367 OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE4) /* gpio 73 => cmt_rst_rq */
368 OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE4) /* gpio 74 => cmt_en */
369 OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE4) /* gpio 75 => cmt_rst */
370 OMAP3_CORE1_IOPAD(0x218e, PIN_OUTPUT | MUX_MODE4) /* gpio 157 => cmt_bsi */
376 OMAP3_CORE1_IOPAD(0x210c, PIN_OUTPUT | MUX_MODE7) /* cam_hs */
377 OMAP3_CORE1_IOPAD(0x210e, PIN_OUTPUT | MUX_MODE7) /* cam_vs */
378 OMAP3_CORE1_IOPAD(0x2110, PIN_OUTPUT | MUX_MODE0) /* cam_xclka */
379 OMAP3_CORE1_IOPAD(0x211e, PIN_OUTPUT | MUX_MODE7) /* cam_d4 */
380 OMAP3_CORE1_IOPAD(0x2122, PIN_INPUT | MUX_MODE0) /* cam_d6 */
381 OMAP3_CORE1_IOPAD(0x2124, PIN_INPUT | MUX_MODE0) /* cam_d7 */
382 OMAP3_CORE1_IOPAD(0x2126, PIN_INPUT | MUX_MODE0) /* cam_d8 */
383 OMAP3_CORE1_IOPAD(0x2128, PIN_INPUT | MUX_MODE0) /* cam_d9 */
384 OMAP3_CORE1_IOPAD(0x212a, PIN_OUTPUT | MUX_MODE7) /* cam_d10 */
385 OMAP3_CORE1_IOPAD(0x212e, PIN_OUTPUT | MUX_MODE7) /* cam_xclkb */
386 OMAP3_CORE1_IOPAD(0x2132, PIN_OUTPUT | MUX_MODE0) /* cam_strobe */
393 pinctrl-0 = <&i2c1_pins>;
398 reg = <0x48>;
411 regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */
419 regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */
426 regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */
433 regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */
440 regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */
447 regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */
455 regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */
463 regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */
471 regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */
501 dma-channel-mask = <0xfffffffc>;
517 linux,keymap = < MATRIX_KEY(0x00, 0x00, KEY_Q)
518 MATRIX_KEY(0x00, 0x01, KEY_O)
519 MATRIX_KEY(0x00, 0x02, KEY_P)
520 MATRIX_KEY(0x00, 0x03, KEY_COMMA)
521 MATRIX_KEY(0x00, 0x04, KEY_BACKSPACE)
522 MATRIX_KEY(0x00, 0x06, KEY_A)
523 MATRIX_KEY(0x00, 0x07, KEY_S)
525 MATRIX_KEY(0x01, 0x00, KEY_W)
526 MATRIX_KEY(0x01, 0x01, KEY_D)
527 MATRIX_KEY(0x01, 0x02, KEY_F)
528 MATRIX_KEY(0x01, 0x03, KEY_G)
529 MATRIX_KEY(0x01, 0x04, KEY_H)
530 MATRIX_KEY(0x01, 0x05, KEY_J)
531 MATRIX_KEY(0x01, 0x06, KEY_K)
532 MATRIX_KEY(0x01, 0x07, KEY_L)
534 MATRIX_KEY(0x02, 0x00, KEY_E)
535 MATRIX_KEY(0x02, 0x01, KEY_DOT)
536 MATRIX_KEY(0x02, 0x02, KEY_UP)
537 MATRIX_KEY(0x02, 0x03, KEY_ENTER)
538 MATRIX_KEY(0x02, 0x05, KEY_Z)
539 MATRIX_KEY(0x02, 0x06, KEY_X)
540 MATRIX_KEY(0x02, 0x07, KEY_C)
541 MATRIX_KEY(0x02, 0x08, KEY_F9)
543 MATRIX_KEY(0x03, 0x00, KEY_R)
544 MATRIX_KEY(0x03, 0x01, KEY_V)
545 MATRIX_KEY(0x03, 0x02, KEY_B)
546 MATRIX_KEY(0x03, 0x03, KEY_N)
547 MATRIX_KEY(0x03, 0x04, KEY_M)
548 MATRIX_KEY(0x03, 0x05, KEY_SPACE)
549 MATRIX_KEY(0x03, 0x06, KEY_SPACE)
550 MATRIX_KEY(0x03, 0x07, KEY_LEFT)
552 MATRIX_KEY(0x04, 0x00, KEY_T)
553 MATRIX_KEY(0x04, 0x01, KEY_DOWN)
554 MATRIX_KEY(0x04, 0x02, KEY_RIGHT)
555 MATRIX_KEY(0x04, 0x04, KEY_LEFTCTRL)
556 MATRIX_KEY(0x04, 0x05, KEY_RIGHTALT)
557 MATRIX_KEY(0x04, 0x06, KEY_LEFTSHIFT)
558 MATRIX_KEY(0x04, 0x08, KEY_F10)
560 MATRIX_KEY(0x05, 0x00, KEY_Y)
561 MATRIX_KEY(0x05, 0x08, KEY_F11)
563 MATRIX_KEY(0x06, 0x00, KEY_U)
565 MATRIX_KEY(0x07, 0x00, KEY_I)
566 MATRIX_KEY(0x07, 0x01, KEY_F7)
567 MATRIX_KEY(0x07, 0x02, KEY_F8)
572 ti,pullups = <0x0>;
573 ti,pulldowns = <0x03ff3f>; /* BIT(0..5) | BIT(8..17) */
578 pinctrl-0 = <&i2c2_pins>;
584 reg = <0x18>;
587 0 /* AIC3X_GPIO1_FUNC_DISABLED */
601 reg = <0x19>;
614 reg = <0x29>;
621 reg = <0x30>;
636 #size-cells = <0>;
638 reg = <0x32>;
639 clock-mode = /bits/ 8 <0>; /* LP55XX_CLOCK_AUTO */
642 led@0 {
643 reg = <0>;
726 reg = <0x55>;
733 reg = <0x60>;
742 reg = <0x63>;
752 reg = <0x6b>;
767 pinctrl-0 = <&i2c3_pins>;
773 reg = <0x1d>;
782 mount-matrix = "-1", "0", "0",
783 "0", "1", "0",
784 "0", "0", "1";
789 reg = <0x3e>;
793 clocks = <&isp 0>;
805 clock-inv = <0>;
816 reg = <0x0c>;
820 #io-channel-cells = <0>;
826 pinctrl-0 = <&mmc1_pins>;
834 pinctrl-0 = <&mmc2_pins>;
848 ranges = <0 0 0x01000000 0x01000000>, /* 16 MB for OneNAND */
849 <1 0 0x02000000 0x01000000>; /* 16 MB for smc91c96 */
851 pinctrl-0 = <&gpmc_pins>;
854 onenand@0,0 {
858 reg = <0 0 0x20000>; /* CS0, offset 0, IO size 128K */
865 * cs0 GPMC_CS_CONFIG1: 0xfb001202
866 * cs0 GPMC_CS_CONFIG2: 0x00111100
867 * cs0 GPMC_CS_CONFIG3: 0x00020200
868 * cs0 GPMC_CS_CONFIG4: 0x11001102
869 * cs0 GPMC_CS_CONFIG5: 0x03101616
870 * cs0 GPMC_CS_CONFIG6: 0x90060000
880 gpmc,cs-on-ns = <0>;
883 gpmc,adv-on-ns = <0>;
888 gpmc,we-on-ns = <0>;
894 gpmc,bus-turnaround-ns = <0>;
895 gpmc,cycle2cycle-delay-ns = <0>;
896 gpmc,wait-monitoring-ns = <0>;
906 partition@0 {
908 reg = <0x00000000 0x00020000>;
913 reg = <0x00020000 0x00060000>;
917 reg = <0x00080000 0x00040000>;
921 reg = <0x000c0000 0x00200000>;
925 reg = <0x002c0000 0x00200000>;
929 reg = <0x004c0000 0x0fb40000>;
938 reg = <1 0 0xf>; /* 16 byte IO range */
941 pinctrl-0 = <ðernet_pins>;
945 gpmc,sync-clk-ps = <0>;
946 gpmc,cs-on-ns = <0>;
949 gpmc,adv-on-ns = <0>;
950 gpmc,adv-rd-off-ns = <0>;
951 gpmc,adv-wr-off-ns = <0>;
956 gpmc,page-burst-access-ns = <0>;
960 gpmc,bus-turnaround-ns = <0>;
961 gpmc,cycle2cycle-delay-ns = <0>;
962 gpmc,wait-monitoring-ns = <0>;
963 gpmc,clk-activation-ns = <0>;
964 gpmc,wr-access-ns = <0>;
976 tsc2005@0 {
979 reg = <0>;
1003 pinctrl-0 = <&acx565akm_pins>;
1018 pinctrl-0 = <&mcspi4_pins>;
1020 wl1251@0 {
1022 pinctrl-0 = <&wl1251_pins>;
1027 reg = <0>;
1048 interface-type = <0>;
1062 pinctrl-0 = <&uart2_pins>;
1077 pinctrl-0 = <&uart3_pins>;
1084 pinctrl-0 = <&dss_sdi_pins>;
1090 #size-cells = <0>;
1122 pinctrl-0 = <&ssi_pins>;
1130 pinctrl-0 = <&modem_pins>;
1132 hsi-channel-ids = <0>, <1>, <2>, <3>;