Lines Matching +full:0 +full:x19000
61 reg = <0x0 0x48211000 0x0 0x1000>,
62 <0x0 0x48212000 0x0 0x2000>,
63 <0x0 0x48214000 0x0 0x2000>,
64 <0x0 0x48216000 0x0 0x2000>;
73 reg = <0x0 0x48281000 0x0 0x1000>;
79 #size-cells = <0>;
81 cpu0: cpu@0 {
84 reg = <0>;
109 opp-supported-hw = <0xFF 0x01>;
119 opp-supported-hw = <0xFF 0x02>;
127 opp-supported-hw = <0xFF 0x04>;
141 clocks = <&l3main1_clkctrl DRA7_L3MAIN1_L3_MAIN_1_CLKCTRL 0>,
142 <&l3instr_clkctrl DRA7_L3INSTR_L3_MAIN_2_CLKCTRL 0>;
145 ranges = <0x0 0x0 0x0 0xc0000000>;
146 dma-ranges = <0x80000000 0x0 0x80000000 0x80000000>;
150 reg = <0x44000000 0x1000000>,
151 <0x45000000 0x1000>;
166 clocks = <&mpu_clkctrl DRA7_MPU_MPU_CLKCTRL 0>;
170 ranges = <0 0x48210000 0x1f0000>;
191 resets = <&prm_l3init 0>;
193 clocks = <&pcie_clkctrl DRA7_PCIE_PCIE1_CLKCTRL 0>,
199 ranges = <0x51000000 0x51000000 0x3000>,
200 <0x20000000 0x20000000 0x10000000>;
207 reg = <0x51000000 0x2000>,
208 <0x51002000 0x14c>,
209 <0x20001000 0x2000>;
211 interrupts = <0 232 0x4>, <0 233 0x4>;
215 ranges = <0x81000000 0 0x00000000 0x20003000 0 0x00010000>,
216 <0x82000000 0 0x20013000 0x20013000 0 0x0ffed000>;
217 bus-range = <0x00 0xff>;
220 linux,pci-domain = <0>;
223 ti,syscon-lane-sel = <&scm_conf_pcie 0x18>;
224 interrupt-map-mask = <0 0 0 7>;
225 interrupt-map = <0 0 0 1 &pcie1_intc 1>,
226 <0 0 0 2 &pcie1_intc 2>,
227 <0 0 0 3 &pcie1_intc 3>,
228 <0 0 0 4 &pcie1_intc 4>;
229 ti,syscon-unaligned-access = <&scm_conf1 0x14 1>;
233 #address-cells = <0>;
239 reg = <0x51000000 0x28>,
240 <0x51002000 0x14c>,
241 <0x51001000 0x28>,
242 <0x20001000 0x10000000>;
244 interrupts = <0 232 0x4>;
250 ti,syscon-unaligned-access = <&scm_conf1 0x14 1>;
251 ti,syscon-lane-sel = <&scm_conf_pcie 0x18>;
264 clocks = <&pcie_clkctrl DRA7_PCIE_PCIE2_CLKCTRL 0>,
273 ranges = <0x51800000 0x51800000 0x3000>,
274 <0x30000000 0x30000000 0x10000000>;
278 reg = <0x51800000 0x2000>,
279 <0x51802000 0x14c>,
280 <0x30001000 0x2000>;
282 interrupts = <0 355 0x4>, <0 356 0x4>;
286 ranges = <0x81000000 0 0x00000000 0x30003000 0 0x00010000>,
287 <0x82000000 0 0x30013000 0x30013000 0 0x0ffed000>;
288 bus-range = <0x00 0xff>;
294 interrupt-map-mask = <0 0 0 7>;
295 interrupt-map = <0 0 0 1 &pcie2_intc 1>,
296 <0 0 0 2 &pcie2_intc 2>,
297 <0 0 0 3 &pcie2_intc 3>,
298 <0 0 0 4 &pcie2_intc 4>;
299 ti,syscon-unaligned-access = <&scm_conf1 0x14 2>;
302 #address-cells = <0>;
310 reg = <0x40300000 0x80000>;
311 ranges = <0x0 0x40300000 0x80000>;
325 sram-hs@0 {
327 reg = <0x0 0x0>;
340 reg = <0x40400000 0x100000>;
341 ranges = <0x0 0x40400000 0x100000>;
349 reg = <0x40500000 0x100000>;
350 ranges = <0x0 0x40500000 0x100000>;
356 reg = <0x4a0021e0 0xc
357 0x4a00232c 0xc
358 0x4a002380 0x2c
359 0x4a0023C0 0x3c
360 0x4a002564 0x8
361 0x4a002574 0x50>;
369 reg = <0x40d00000 0x100>;
374 reg = <0x4844a000 0x0d1c>;
376 #size-cells = <0>;
382 reg = <0x43300000 0x4>,
383 <0x43300010 0x4>;
391 clocks = <&l3main1_clkctrl DRA7_L3MAIN1_TPCC_CLKCTRL 0>;
395 ranges = <0x0 0x43300000 0x100000>;
397 edma: dma@0 {
399 reg = <0 0x100000>;
409 ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 0>;
422 reg = <0x43400000 0x4>,
423 <0x43400010 0x4>;
431 clocks = <&l3main1_clkctrl DRA7_L3MAIN1_TPTC0_CLKCTRL 0>;
435 ranges = <0x0 0x43400000 0x100000>;
437 edma_tptc0: dma@0 {
439 reg = <0 0x100000>;
447 reg = <0x43500000 0x4>,
448 <0x43500010 0x4>;
456 clocks = <&l3main1_clkctrl DRA7_L3MAIN1_TPTC1_CLKCTRL 0>;
460 ranges = <0x0 0x43500000 0x100000>;
462 edma_tptc1: dma@0 {
464 reg = <0 0x100000>;
472 reg = <0x4e000000 0x4>,
473 <0x4e000010 0x4>;
478 ranges = <0x0 0x4e000000 0x2000000>;
482 dmm@0 {
484 reg = <0 0x800>;
491 reg = <0x58820000 0x10000>;
495 resets = <&prm_ipu 0>, <&prm_ipu 1>;
496 clocks = <&ipu1_clkctrl DRA7_IPU1_MMU_IPU1_CLKCTRL 0>;
502 reg = <0x55020000 0x10000>;
506 resets = <&prm_core 0>, <&prm_core 1>;
507 clocks = <&ipu2_clkctrl DRA7_IPU2_MMU_IPU2_CLKCTRL 0>;
513 reg = <0x40800000 0x48000>,
514 <0x40e00000 0x8000>,
515 <0x40f00000 0x8000>;
517 ti,bootreg = <&scm_conf 0x55c 10>;
520 resets = <&prm_dsp1 0>;
521 clocks = <&dsp1_clkctrl DRA7_DSP1_MMU0_DSP1_CLKCTRL 0>;
527 reg = <0x40d01000 0x4>,
528 <0x40d01010 0x4>,
529 <0x40d01014 0x4>;
537 clocks = <&dsp1_clkctrl DRA7_DSP1_MMU0_DSP1_CLKCTRL 0>;
541 ranges = <0x0 0x40d01000 0x1000>;
545 mmu0_dsp1: mmu@0 {
547 reg = <0x0 0x100>;
549 #iommu-cells = <0>;
550 ti,syscon-mmuconfig = <&dsp1_system 0x0>;
556 reg = <0x40d02000 0x4>,
557 <0x40d02010 0x4>,
558 <0x40d02014 0x4>;
566 clocks = <&dsp1_clkctrl DRA7_DSP1_MMU0_DSP1_CLKCTRL 0>;
570 ranges = <0x0 0x40d02000 0x1000>;
574 mmu1_dsp1: mmu@0 {
576 reg = <0x0 0x100>;
578 #iommu-cells = <0>;
579 ti,syscon-mmuconfig = <&dsp1_system 0x1>;
585 reg = <0x58882000 0x4>,
586 <0x58882010 0x4>,
587 <0x58882014 0x4>;
595 clocks = <&ipu1_clkctrl DRA7_IPU1_MMU_IPU1_CLKCTRL 0>;
601 ranges = <0x0 0x58882000 0x100>;
603 mmu_ipu1: mmu@0 {
605 reg = <0x0 0x100>;
607 #iommu-cells = <0>;
614 reg = <0x55082000 0x4>,
615 <0x55082010 0x4>,
616 <0x55082014 0x4>;
624 clocks = <&ipu2_clkctrl DRA7_IPU2_MMU_IPU2_CLKCTRL 0>;
630 ranges = <0x0 0x55082000 0x100>;
632 mmu_ipu2: mmu@0 {
634 reg = <0x0 0x100>;
636 #iommu-cells = <0>;
644 #address-cells = <0>;
645 #size-cells = <0>;
650 reg = <0x4ae07ddc 0x4>, <0x4ae07de0 0x4>,
651 <0x4ae06014 0x4>, <0x4a003b20 0xc>,
652 <0x4ae0c158 0x4>;
656 ti,tranxdone-status-mask = <0x80>;
658 ti,ldovbb-override-mask = <0x400>;
660 ti,ldovbb-vset-mask = <0x1F>;
668 1060000 0 0x0 0 0x02000000 0x01F00000
669 1160000 0 0x4 0 0x02000000 0x01F00000
670 1210000 0 0x8 0 0x02000000 0x01F00000
677 #address-cells = <0>;
678 #size-cells = <0>;
683 reg = <0x4ae07e34 0x4>, <0x4ae07e24 0x4>,
684 <0x4ae06010 0x4>, <0x4a0025cc 0xc>,
685 <0x4a002470 0x4>;
689 ti,tranxdone-status-mask = <0x40000000>;
691 ti,ldovbb-override-mask = <0x400>;
693 ti,ldovbb-vset-mask = <0x1F>;
701 1055000 0 0x0 0 0x02000000 0x01F00000
702 1150000 0 0x4 0 0x02000000 0x01F00000
703 1250000 0 0x8 0 0x02000000 0x01F00000
710 #address-cells = <0>;
711 #size-cells = <0>;
716 reg = <0x4ae07e30 0x4>, <0x4ae07e20 0x4>,
717 <0x4ae06010 0x4>, <0x4a0025e0 0xc>,
718 <0x4a00246c 0x4>;
722 ti,tranxdone-status-mask = <0x20000000>;
724 ti,ldovbb-override-mask = <0x400>;
726 ti,ldovbb-vset-mask = <0x1F>;
734 1055000 0 0x0 0 0x02000000 0x01F00000
735 1150000 0 0x4 0 0x02000000 0x01F00000
736 1250000 0 0x8 0 0x02000000 0x01F00000
743 #address-cells = <0>;
744 #size-cells = <0>;
749 reg = <0x4ae07de4 0x4>, <0x4ae07de8 0x4>,
750 <0x4ae06010 0x4>, <0x4a003b08 0xc>,
751 <0x4ae0c154 0x4>;
755 ti,tranxdone-status-mask = <0x10000000>;
757 ti,ldovbb-override-mask = <0x400>;
759 ti,ldovbb-vset-mask = <0x1F>;
767 1090000 0 0x0 0 0x02000000 0x01F00000
768 1210000 0 0x4 0 0x02000000 0x01F00000
769 1280000 0 0x8 0 0x02000000 0x01F00000
775 reg = <0x4b300000 0x4>,
776 <0x4b300010 0x4>;
782 clocks = <&l4per2_clkctrl DRA7_L4PER2_QSPI_CLKCTRL 0>;
786 ranges = <0x0 0x4b300000 0x1000>,
787 <0x5c000000 0x5c000000 0x4000000>;
789 qspi: spi@0 {
791 reg = <0 0x100>,
792 <0x5c000000 0x4000000>;
794 syscon-chipselects = <&scm_conf 0x558>;
796 #size-cells = <0>;
810 reg = <0x50000000 4>,
811 <0x50000010 4>,
812 <0x50000014 4>;
818 clocks = <&l3main1_clkctrl DRA7_L3MAIN1_GPMC_CLKCTRL 0>;
822 ranges = <0x50000000 0x50000000 0x00001000>, /* regs */
823 <0x00000000 0x00000000 0x40000000>; /* data */
827 reg = <0x50000000 0x37c>; /* device IO registers */
829 dmas = <&edma_xbar 4 0>;
845 reg = <0x5600fe00 0x4>,
846 <0x5600fe10 0x4>;
854 clocks = <&gpu_clkctrl DRA7_GPU_CLKCTRL 0>;
858 ranges = <0 0x56000000 0x2000000>;
863 reg = <0x4a002a48 0x130>;
870 ti,irqs-reserved = <0 1 2 3 5 6 131 132>;
872 ti,irqs-safe-map = <0>;
877 reg = <0x58000000 4>,
878 <0x58000014 4>;
881 clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 0>,
888 ranges = <0 0x58000000 0x800000>;
890 dss: dss@0 {
896 syscon-pll-ctrl = <&scm_conf 0x538>;
899 ranges = <0 0 0x800000>;
903 reg = <0x1000 0x4>,
904 <0x1010 0x4>,
905 <0x1014 0x4>;
922 ranges = <0 0x1000 0x1000>;
924 dispc@0 {
926 reg = <0 0x1000>;
931 syscon-pol = <&scm_conf 0x534>;
937 reg = <0x40000 0x4>,
938 <0x40010 0x4>;
950 ranges = <0 0x40000 0x40000>;
952 hdmi: encoder@0 {
954 reg = <0 0x200>,
955 <0x200 0x80>,
956 <0x300 0x80>,
957 <0x20000 0x19000>;
973 reg = <0x59000020 0x4>;
975 clocks = <&dss_clkctrl DRA7_DSS_BB2D_CLKCTRL 0>;
979 ranges = <0x0 0x59000000 0x1000>;
981 bb2d: gpu@0 {
983 reg = <0x0 0x700>;
985 clocks = <&dss_clkctrl DRA7_DSS_BB2D_CLKCTRL 0>;
992 reg = <0x4b500080 0x4>,
993 <0x4b500084 0x4>,
994 <0x4b500088 0x4>;
1004 clocks = <&l4sec_clkctrl DRA7_L4SEC_AES1_CLKCTRL 0>;
1008 ranges = <0x0 0x4b500000 0x1000>;
1010 aes1: aes@0 {
1012 reg = <0 0xa0>;
1014 dmas = <&edma_xbar 111 0>, <&edma_xbar 110 0>;
1023 reg = <0x4b700080 0x4>,
1024 <0x4b700084 0x4>,
1025 <0x4b700088 0x4>;
1035 clocks = <&l4sec_clkctrl DRA7_L4SEC_AES2_CLKCTRL 0>;
1039 ranges = <0x0 0x4b700000 0x1000>;
1041 aes2: aes@0 {
1043 reg = <0 0xa0>;
1045 dmas = <&edma_xbar 114 0>, <&edma_xbar 113 0>;
1054 reg = <0x4b101100 0x4>,
1055 <0x4b101110 0x4>,
1056 <0x4b101114 0x4>;
1065 clocks = <&l4sec_clkctrl DRA7_L4SEC_SHAM_CLKCTRL 0>;
1069 ranges = <0x0 0x4b101000 0x1000>;
1071 sham1: sham@0 {
1073 reg = <0 0x300>;
1075 dmas = <&edma_xbar 119 0>;
1084 reg = <0x42701100 0x4>,
1085 <0x42701110 0x4>,
1086 <0x42701114 0x4>;
1095 clocks = <&l4sec_clkctrl DRA7_L4SEC_SHAM2_CLKCTRL 0>;
1099 ranges = <0x0 0x42701000 0x1000>;
1101 sham2: sham@0 {
1103 reg = <0 0x300>;
1105 dmas = <&edma_xbar 165 0>;
1114 reg = <0x5a05a400 0x4>,
1115 <0x5a05a410 0x4>;
1126 clocks = <&iva_clkctrl DRA7_IVA_CLKCTRL 0>;
1130 ranges = <0x5a000000 0x5a000000 0x1000000>,
1131 <0x5b000000 0x5b000000 0x1000000>;
1140 reg = <0x4a003b20 0xc>;
1143 1060000 0x0
1144 1160000 0x4
1145 1210000 0x8
1164 coefficients = <0 2000>;
1168 coefficients = <0 2000>;
1172 coefficients = <0 2000>;
1176 coefficients = <0 2000>;
1180 coefficients = <0 2000>;
1209 reg = <0x300 0x100>;
1210 #power-domain-cells = <0>;
1215 reg = <0x400 0x100>;
1217 #power-domain-cells = <0>;
1222 reg = <0x500 0x100>;
1224 #power-domain-cells = <0>;
1229 reg = <0x628 0xd8>;
1230 #power-domain-cells = <0>;
1235 reg = <0x700 0x100>;
1237 #power-domain-cells = <0>;
1242 reg = <0xf00 0x100>;
1244 #power-domain-cells = <0>;
1249 reg = <0x1000 0x100>;
1250 #power-domain-cells = <0>;
1255 reg = <0x1100 0x100>;
1256 #power-domain-cells = <0>;
1261 reg = <0x1200 0x100>;
1262 #power-domain-cells = <0>;
1267 reg = <0x1300 0x100>;
1269 #power-domain-cells = <0>;
1274 reg = <0x1400 0x100>;
1275 #power-domain-cells = <0>;
1280 reg = <0x1600 0x100>;
1281 #power-domain-cells = <0>;
1286 reg = <0x1724 0x100>;
1287 #power-domain-cells = <0>;
1292 reg = <0x1b00 0x40>;
1294 #power-domain-cells = <0>;
1299 reg = <0x1b40 0x40>;
1300 #power-domain-cells = <0>;
1305 reg = <0x1b80 0x40>;
1306 #power-domain-cells = <0>;
1311 reg = <0x1bc0 0x40>;
1312 #power-domain-cells = <0>;
1317 reg = <0x1c00 0x60>;
1318 #power-domain-cells = <0>;
1323 reg = <0x1c60 0x20>;
1324 #power-domain-cells = <0>;
1329 reg = <0x1c80 0x80>;
1330 #power-domain-cells = <0>;
1338 timer@0 {
1348 timer@0 {
1357 timer@0 {