Lines Matching +full:0 +full:x2e0
12 reg = <0x40 0x40>;
24 reg = <0x80 0x30>;
35 reg = <0xb0 0x30>;
46 reg = <0xe0 0x30>;
57 reg = <0x110 0x30>;
68 reg = <0x140 0x30>;
79 reg = <0x170 0x30>;
90 reg = <0x1a0 0x30>;
101 reg = <0x1d0 0x30>;
112 reg = <0x200 0x30>;
123 reg = <0x230 0x30>;
134 reg = <0x260 0x30>;
145 reg = <0x290 0x30>;
156 #clock-cells = <0>;
161 reg = <0x2e0>;
165 #clock-cells = <0>;
170 reg = <0x2e0>;
175 #clock-cells = <0>;
181 reg = <0x2e8>;
186 #clock-cells = <0>;
192 #clock-cells = <0>;
195 ti,bit-shift = <0>;
196 reg = <0x02f0>;
202 #clock-cells = <0>;
206 reg = <0x0040>;
211 #clock-cells = <0>;
218 #clock-cells = <0>;
225 #clock-cells = <0>;
227 clock-frequency = <0>;
231 #clock-cells = <0>;
237 #clock-cells = <0>;
243 #clock-cells = <0>;
251 #clock-cells = <0>;
259 #clock-cells = <0>;
262 ti,bit-shift = <0>;
263 reg = <0x0040>;
268 #clock-cells = <0>;
277 #clock-cells = <0>;
286 #clock-cells = <0>;
295 #clock-cells = <0>;
303 #clock-cells = <0>;
312 reg = <0x324>;
314 #clock-cells = <0>;
319 #clock-cells = <0>;
325 #clock-cells = <0>;
331 #clock-cells = <0>;
340 reg = <0x500 0x100>;
343 ranges = <0 0x500 0x100>;
345 default_clkctrl: clk@0 {
347 reg = <0x0 0x5c>;
354 reg = <0x1400 0x300>;
357 ranges = <0 0x1400 0x300>;
359 alwon_clkctrl: clk@0 {
361 reg = <0x0 0x228>;
368 reg = <0x15d4 0x4>;
371 ranges = <0 0x15d4 0x4>;
373 alwon_ethernet_clkctrl: clk@0 {
375 reg = <0 0x4>;