Lines Matching +full:0 +full:x4c000
1 &l4_wkup { /* 0x44c00000 */
4 clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_L4_WKUP_CLKCTRL 0>;
6 reg = <0x44c00000 0x800>,
7 <0x44c00800 0x800>,
8 <0x44c01000 0x400>,
9 <0x44c01400 0x400>;
13 ranges = <0x00000000 0x44c00000 0x100000>, /* segment 0 */
14 <0x00100000 0x44d00000 0x100000>, /* segment 1 */
15 <0x00200000 0x44e00000 0x100000>; /* segment 2 */
17 segment@0 { /* 0x44c00000 */
21 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
22 <0x00000800 0x00000800 0x000800>, /* ap 1 */
23 <0x00001000 0x00001000 0x000400>, /* ap 2 */
24 <0x00001400 0x00001400 0x000400>; /* ap 3 */
27 segment@100000 { /* 0x44d00000 */
31 ranges = <0x00000000 0x00100000 0x004000>, /* ap 4 */
32 <0x00004000 0x00104000 0x001000>, /* ap 5 */
33 <0x00080000 0x00180000 0x002000>, /* ap 6 */
34 <0x00082000 0x00182000 0x001000>; /* ap 7 */
36 target-module@0 { /* 0x44d00000, ap 4 28.0 */
38 reg = <0x0 0x4>;
40 clocks = <&l4_wkup_aon_clkctrl AM3_L4_WKUP_AON_WKUP_M3_CLKCTRL 0>;
44 ranges = <0x00000000 0x00000000 0x4000>,
45 <0x00080000 0x00080000 0x2000>;
47 wkup_m3: cpu@0 {
49 reg = <0x00000000 0x4000>,
50 <0x00080000 0x2000>;
59 segment@200000 { /* 0x44e00000 */
63 ranges = <0x00000000 0x00200000 0x002000>, /* ap 8 */
64 <0x00002000 0x00202000 0x001000>, /* ap 9 */
65 <0x00003000 0x00203000 0x001000>, /* ap 10 */
66 <0x00004000 0x00204000 0x001000>, /* ap 11 */
67 <0x00005000 0x00205000 0x001000>, /* ap 12 */
68 <0x00006000 0x00206000 0x001000>, /* ap 13 */
69 <0x00007000 0x00207000 0x001000>, /* ap 14 */
70 <0x00008000 0x00208000 0x001000>, /* ap 15 */
71 <0x00009000 0x00209000 0x001000>, /* ap 16 */
72 <0x0000a000 0x0020a000 0x001000>, /* ap 17 */
73 <0x0000b000 0x0020b000 0x001000>, /* ap 18 */
74 <0x0000c000 0x0020c000 0x001000>, /* ap 19 */
75 <0x0000d000 0x0020d000 0x001000>, /* ap 20 */
76 <0x0000f000 0x0020f000 0x001000>, /* ap 21 */
77 <0x00010000 0x00210000 0x010000>, /* ap 22 */
78 <0x00020000 0x00220000 0x010000>, /* ap 23 */
79 <0x00030000 0x00230000 0x001000>, /* ap 24 */
80 <0x00031000 0x00231000 0x001000>, /* ap 25 */
81 <0x00032000 0x00232000 0x001000>, /* ap 26 */
82 <0x00033000 0x00233000 0x001000>, /* ap 27 */
83 <0x00034000 0x00234000 0x001000>, /* ap 28 */
84 <0x00035000 0x00235000 0x001000>, /* ap 29 */
85 <0x00036000 0x00236000 0x001000>, /* ap 30 */
86 <0x00037000 0x00237000 0x001000>, /* ap 31 */
87 <0x00038000 0x00238000 0x001000>, /* ap 32 */
88 <0x00039000 0x00239000 0x001000>, /* ap 33 */
89 <0x0003a000 0x0023a000 0x001000>, /* ap 34 */
90 <0x0003e000 0x0023e000 0x001000>, /* ap 35 */
91 <0x0003f000 0x0023f000 0x001000>, /* ap 36 */
92 <0x0000e000 0x0020e000 0x001000>, /* ap 37 */
93 <0x00040000 0x00240000 0x040000>, /* ap 38 */
94 <0x00080000 0x00280000 0x001000>; /* ap 39 */
96 target-module@0 { /* 0x44e00000, ap 8 58.0 */
98 reg = <0 0x4>;
102 ranges = <0x0 0x0 0x2000>;
104 prcm: prcm@0 {
106 reg = <0 0x2000>;
109 ranges = <0 0 0x2000>;
113 #size-cells = <0>;
121 target-module@3000 { /* 0x44e03000, ap 10 0a.0 */
126 ranges = <0x0 0x3000 0x1000>;
129 target-module@5000 { /* 0x44e05000, ap 12 30.0 */
134 ranges = <0x0 0x5000 0x1000>;
137 gpio0_target: target-module@7000 { /* 0x44e07000, ap 14 20.0 */
139 reg = <0x7000 0x4>,
140 <0x7010 0x4>,
141 <0x7114 0x4>;
152 clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_GPIO1_CLKCTRL 0>,
157 ranges = <0x0 0x7000 0x1000>;
159 gpio0: gpio@0 {
161 gpio-ranges = <&am33xx_pinmux 0 82 8>,
177 reg = <0x0 0x1000>;
182 target-module@9000 { /* 0x44e09000, ap 16 04.0 */
184 reg = <0x9050 0x4>,
185 <0x9054 0x4>,
186 <0x9058 0x4>;
196 clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_UART1_CLKCTRL 0>;
200 ranges = <0x0 0x9000 0x1000>;
202 uart0: serial@0 {
205 reg = <0x0 0x1000>;
208 dmas = <&edma 26 0>, <&edma 27 0>;
213 target-module@b000 { /* 0x44e0b000, ap 18 48.0 */
215 reg = <0xb000 0x8>,
216 <0xb010 0x8>,
217 <0xb090 0x8>;
229 clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_I2C1_CLKCTRL 0>;
233 ranges = <0x0 0xb000 0x1000>;
235 i2c0: i2c@0 {
238 #size-cells = <0>;
239 reg = <0x0 0x1000>;
245 target-module@d000 { /* 0x44e0d000, ap 20 38.0 */
247 reg = <0xd000 0x4>,
248 <0xd010 0x4>;
255 clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_ADC_TSC_CLKCTRL 0>;
259 ranges = <0x00000000 0x0000d000 0x00001000>,
260 <0x00001000 0x0000e000 0x00001000>;
262 tscadc: tscadc@0 {
264 reg = <0x0 0x1000>;
269 dmas = <&edma 53 0>, <&edma 57 0>;
282 target-module@10000 { /* 0x44e10000, ap 22 0c.0 */
284 reg = <0x10000 0x4>;
286 clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_CONTROL_CLKCTRL 0>;
291 ranges = <0x00000000 0x00010000 0x00010000>,
292 <0x00010000 0x00020000 0x00010000>;
294 scm: scm@0 {
296 reg = <0x0 0x2000>;
300 ranges = <0 0 0x2000>;
304 reg = <0x800 0x238>;
307 pinctrl-single,function-mask = <0x7f>;
310 scm_conf: scm_conf@0 {
312 reg = <0x0 0x800>;
315 ranges = <0 0 0x800>;
319 reg = <0x650 0x4>;
325 #size-cells = <0>;
331 reg = <0x620 0x10>,
332 <0x648 0x4>;
338 reg = <0x1324 0x24>;
346 reg = <0xf90 0x40>;
357 timer1_target: target-module@31000 { /* 0x44e31000, ap 25 40.0 */
359 reg = <0x31000 0x4>,
360 <0x31010 0x4>,
361 <0x31014 0x4>;
371 clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_TIMER1_CLKCTRL 0>;
375 ranges = <0x0 0x31000 0x1000>;
377 timer1: timer@0 {
379 reg = <0x0 0x400>;
387 target-module@33000 { /* 0x44e33000, ap 27 18.0 */
392 ranges = <0x0 0x33000 0x1000>;
395 target-module@35000 { /* 0x44e35000, ap 29 50.0 */
397 reg = <0x35000 0x4>,
398 <0x35010 0x4>,
399 <0x35014 0x4>;
409 clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_WD_TIMER2_CLKCTRL 0>;
413 ranges = <0x0 0x35000 0x1000>;
415 wdt2: wdt@0 {
417 reg = <0x0 0x1000>;
422 target-module@37000 { /* 0x44e37000, ap 31 08.0 */
427 ranges = <0x0 0x37000 0x1000>;
430 target-module@39000 { /* 0x44e39000, ap 33 02.0 */
435 ranges = <0x0 0x39000 0x1000>;
438 target-module@3e000 { /* 0x44e3e000, ap 35 60.0 */
440 reg = <0x3e074 0x4>,
441 <0x3e078 0x4>;
449 clocks = <&l4_rtc_clkctrl AM3_L4_RTC_RTC_CLKCTRL 0>;
453 ranges = <0x0 0x3e000 0x1000>;
455 rtc: rtc@0 {
457 reg = <0x0 0x1000>;
463 target-module@40000 { /* 0x44e40000, ap 38 68.0 */
468 ranges = <0x0 0x40000 0x40000>;
473 &l4_fw { /* 0x47c00000 */
475 reg = <0x47c00000 0x800>,
476 <0x47c00800 0x800>,
477 <0x47c01000 0x400>;
481 ranges = <0x00000000 0x47c00000 0x1000000>; /* segment 0 */
483 segment@0 { /* 0x47c00000 */
487 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
488 <0x00000800 0x00000800 0x000800>, /* ap 1 */
489 <0x00001000 0x00001000 0x000400>, /* ap 2 */
490 <0x0000c000 0x0000c000 0x001000>, /* ap 3 */
491 <0x0000d000 0x0000d000 0x001000>, /* ap 4 */
492 <0x0000e000 0x0000e000 0x001000>, /* ap 5 */
493 <0x0000f000 0x0000f000 0x001000>, /* ap 6 */
494 <0x00010000 0x00010000 0x001000>, /* ap 7 */
495 <0x00011000 0x00011000 0x001000>, /* ap 8 */
496 <0x0001a000 0x0001a000 0x001000>, /* ap 9 */
497 <0x0001b000 0x0001b000 0x001000>, /* ap 10 */
498 <0x00024000 0x00024000 0x001000>, /* ap 11 */
499 <0x00025000 0x00025000 0x001000>, /* ap 12 */
500 <0x00026000 0x00026000 0x001000>, /* ap 13 */
501 <0x00027000 0x00027000 0x001000>, /* ap 14 */
502 <0x00030000 0x00030000 0x001000>, /* ap 15 */
503 <0x00031000 0x00031000 0x001000>, /* ap 16 */
504 <0x00038000 0x00038000 0x001000>, /* ap 17 */
505 <0x00039000 0x00039000 0x001000>, /* ap 18 */
506 <0x0003a000 0x0003a000 0x001000>, /* ap 19 */
507 <0x0003b000 0x0003b000 0x001000>, /* ap 20 */
508 <0x0003e000 0x0003e000 0x001000>, /* ap 21 */
509 <0x0003f000 0x0003f000 0x001000>, /* ap 22 */
510 <0x0003c000 0x0003c000 0x001000>, /* ap 23 */
511 <0x00040000 0x00040000 0x001000>, /* ap 24 */
512 <0x00046000 0x00046000 0x001000>, /* ap 25 */
513 <0x00047000 0x00047000 0x001000>, /* ap 26 */
514 <0x00044000 0x00044000 0x001000>, /* ap 27 */
515 <0x00045000 0x00045000 0x001000>, /* ap 28 */
516 <0x00028000 0x00028000 0x001000>, /* ap 29 */
517 <0x00029000 0x00029000 0x001000>, /* ap 30 */
518 <0x00032000 0x00032000 0x001000>, /* ap 31 */
519 <0x00033000 0x00033000 0x001000>, /* ap 32 */
520 <0x0003d000 0x0003d000 0x001000>, /* ap 33 */
521 <0x00041000 0x00041000 0x001000>, /* ap 34 */
522 <0x00042000 0x00042000 0x001000>, /* ap 35 */
523 <0x00043000 0x00043000 0x001000>, /* ap 36 */
524 <0x00014000 0x00014000 0x001000>, /* ap 37 */
525 <0x00015000 0x00015000 0x001000>; /* ap 38 */
527 target-module@c000 { /* 0x47c0c000, ap 3 04.0 */
532 ranges = <0x0 0xc000 0x1000>;
535 target-module@e000 { /* 0x47c0e000, ap 5 0c.0 */
540 ranges = <0x0 0xe000 0x1000>;
543 target-module@10000 { /* 0x47c10000, ap 7 20.0 */
548 ranges = <0x0 0x10000 0x1000>;
551 target-module@14000 { /* 0x47c14000, ap 37 3c.0 */
556 ranges = <0x0 0x14000 0x1000>;
559 target-module@1a000 { /* 0x47c1a000, ap 9 08.0 */
564 ranges = <0x0 0x1a000 0x1000>;
567 target-module@24000 { /* 0x47c24000, ap 11 28.0 */
572 ranges = <0x0 0x24000 0x1000>;
575 target-module@26000 { /* 0x47c26000, ap 13 30.0 */
580 ranges = <0x0 0x26000 0x1000>;
583 target-module@28000 { /* 0x47c28000, ap 29 40.0 */
588 ranges = <0x0 0x28000 0x1000>;
591 target-module@30000 { /* 0x47c30000, ap 15 14.0 */
596 ranges = <0x0 0x30000 0x1000>;
599 target-module@32000 { /* 0x47c32000, ap 31 06.0 */
604 ranges = <0x0 0x32000 0x1000>;
607 target-module@38000 { /* 0x47c38000, ap 17 18.0 */
612 ranges = <0x0 0x38000 0x1000>;
615 target-module@3a000 { /* 0x47c3a000, ap 19 1c.0 */
620 ranges = <0x0 0x3a000 0x1000>;
623 target-module@3c000 { /* 0x47c3c000, ap 23 38.0 */
628 ranges = <0x0 0x3c000 0x1000>;
631 target-module@3e000 { /* 0x47c3e000, ap 21 10.0 */
636 ranges = <0x0 0x3e000 0x1000>;
639 target-module@40000 { /* 0x47c40000, ap 24 02.0 */
644 ranges = <0x0 0x40000 0x1000>;
647 target-module@42000 { /* 0x47c42000, ap 35 34.0 */
652 ranges = <0x0 0x42000 0x1000>;
655 target-module@44000 { /* 0x47c44000, ap 27 24.0 */
660 ranges = <0x0 0x44000 0x1000>;
663 target-module@46000 { /* 0x47c46000, ap 25 2c.0 */
668 ranges = <0x0 0x46000 0x1000>;
673 &l4_fast { /* 0x4a000000 */
676 clocks = <&l4hs_clkctrl AM3_L4HS_L4_HS_CLKCTRL 0>;
678 reg = <0x4a000000 0x800>,
679 <0x4a000800 0x800>,
680 <0x4a001000 0x400>;
684 ranges = <0x00000000 0x4a000000 0x1000000>; /* segment 0 */
686 segment@0 { /* 0x4a000000 */
690 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
691 <0x00000800 0x00000800 0x000800>, /* ap 1 */
692 <0x00001000 0x00001000 0x000400>, /* ap 2 */
693 <0x00100000 0x00100000 0x008000>, /* ap 3 */
694 <0x00108000 0x00108000 0x001000>, /* ap 4 */
695 <0x00180000 0x00180000 0x020000>, /* ap 5 */
696 <0x001a0000 0x001a0000 0x001000>, /* ap 6 */
697 <0x00200000 0x00200000 0x080000>, /* ap 7 */
698 <0x00280000 0x00280000 0x001000>, /* ap 8 */
699 <0x00300000 0x00300000 0x080000>, /* ap 9 */
700 <0x00380000 0x00380000 0x001000>; /* ap 10 */
702 target-module@100000 { /* 0x4a100000, ap 3 08.0 */
704 reg = <0x101200 0x4>,
705 <0x101208 0x4>,
706 <0x101204 0x4>;
708 ti,sysc-mask = <0>;
714 clocks = <&cpsw_125mhz_clkctrl AM3_CPSW_125MHZ_CPGMAC0_CLKCTRL 0>;
718 ranges = <0x0 0x100000 0x8000>;
720 mac: ethernet@0 {
726 bd_ram_size = <0x2000>;
727 mac_control = <0x20>;
729 active_slave = <0>;
730 cpts_clock_mult = <0x80000000>;
732 reg = <0x0 0x800
733 0x1200 0x100>;
743 ranges = <0 0 0x8000>;
749 clocks = <&cpsw_125mhz_clkctrl AM3_CPSW_125MHZ_CPGMAC0_CLKCTRL 0>;
752 #size-cells = <0>;
754 reg = <0x1000 0x100>;
771 mac_sw: switch@0 {
773 reg = <0x0 0x4000>;
774 ranges = <0 0 0x4000>;
787 #size-cells = <0>;
809 #size-cells = <0>;
811 reg = <0x1000 0x100>;
821 target-module@180000 { /* 0x4a180000, ap 5 10.0 */
826 ranges = <0x0 0x180000 0x20000>;
829 target-module@200000 { /* 0x4a200000, ap 7 02.0 */
834 ranges = <0x0 0x200000 0x80000>;
837 pruss_tm: target-module@300000 { /* 0x4a300000, ap 9 04.0 */
839 reg = <0x326000 0x4>,
840 <0x326004 0x4>;
850 clocks = <&pruss_ocp_clkctrl AM3_PRUSS_OCP_PRUSS_CLKCTRL 0>;
856 ranges = <0x0 0x300000 0x80000>;
859 pruss: pruss@0 {
861 reg = <0x0 0x80000>;
866 pruss_mem: memories@0 {
867 reg = <0x0 0x2000>,
868 <0x2000 0x2000>,
869 <0x10000 0x3000>;
876 reg = <0x26000 0x2000>;
879 ranges = <0x0 0x26000 0x2000>;
883 #size-cells = <0>;
886 reg = <0x30>;
887 #clock-cells = <0>;
896 reg = <0x32000 0x58>;
901 reg = <0x20000 0x2000>;
913 reg = <0x34000 0x2000>,
914 <0x22000 0x400>,
915 <0x22400 0x100>;
922 reg = <0x38000 0x2000>,
923 <0x24000 0x400>,
924 <0x24400 0x100>;
931 reg = <0x32400 0x90>;
936 #size-cells = <0>;
944 &l4_mpuss { /* 0x4b140000 */
946 reg = <0x4b144400 0x100>,
947 <0x4b144800 0x400>;
951 ranges = <0x00000000 0x4b140000 0x008000>; /* segment 0 */
953 segment@0 { /* 0x4b140000 */
957 ranges = <0x00004800 0x00004800 0x000400>, /* ap 0 */
958 <0x00001000 0x00001000 0x001000>, /* ap 1 */
959 <0x00002000 0x00002000 0x001000>, /* ap 2 */
960 <0x00004000 0x00004000 0x000400>, /* ap 3 */
961 <0x00005000 0x00005000 0x000400>, /* ap 4 */
962 <0x00000000 0x00000000 0x001000>, /* ap 5 */
963 <0x00003000 0x00003000 0x001000>, /* ap 6 */
964 <0x00000800 0x00000800 0x000800>; /* ap 7 */
966 target-module@0 { /* 0x4b140000, ap 5 02.2 */
971 ranges = <0x00000000 0x00000000 0x00001000>,
972 <0x00001000 0x00001000 0x00001000>,
973 <0x00002000 0x00002000 0x00001000>;
976 target-module@3000 { /* 0x4b143000, ap 6 04.0 */
981 ranges = <0x0 0x3000 0x1000>;
986 &l4_per { /* 0x48000000 */
989 clocks = <&l4ls_clkctrl AM3_L4LS_L4_LS_CLKCTRL 0>;
991 reg = <0x48000000 0x800>,
992 <0x48000800 0x800>,
993 <0x48001000 0x400>,
994 <0x48001400 0x400>,
995 <0x48001800 0x400>,
996 <0x48001c00 0x400>;
1000 ranges = <0x00000000 0x48000000 0x100000>, /* segment 0 */
1001 <0x00100000 0x48100000 0x100000>, /* segment 1 */
1002 <0x00200000 0x48200000 0x100000>, /* segment 2 */
1003 <0x00300000 0x48300000 0x100000>, /* segment 3 */
1004 <0x46000000 0x46000000 0x400000>, /* l3 data port */
1005 <0x46400000 0x46400000 0x400000>; /* l3 data port */
1007 segment@0 { /* 0x48000000 */
1011 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
1012 <0x00000800 0x00000800 0x000800>, /* ap 1 */
1013 <0x00001000 0x00001000 0x000400>, /* ap 2 */
1014 <0x00001400 0x00001400 0x000400>, /* ap 3 */
1015 <0x00001800 0x00001800 0x000400>, /* ap 4 */
1016 <0x00001c00 0x00001c00 0x000400>, /* ap 5 */
1017 <0x00008000 0x00008000 0x001000>, /* ap 6 */
1018 <0x00009000 0x00009000 0x001000>, /* ap 7 */
1019 <0x00016000 0x00016000 0x001000>, /* ap 8 */
1020 <0x00017000 0x00017000 0x001000>, /* ap 9 */
1021 <0x00022000 0x00022000 0x001000>, /* ap 10 */
1022 <0x00023000 0x00023000 0x001000>, /* ap 11 */
1023 <0x00024000 0x00024000 0x001000>, /* ap 12 */
1024 <0x00025000 0x00025000 0x001000>, /* ap 13 */
1025 <0x0002a000 0x0002a000 0x001000>, /* ap 14 */
1026 <0x0002b000 0x0002b000 0x001000>, /* ap 15 */
1027 <0x00038000 0x00038000 0x002000>, /* ap 16 */
1028 <0x0003a000 0x0003a000 0x001000>, /* ap 17 */
1029 <0x00014000 0x00014000 0x001000>, /* ap 18 */
1030 <0x00015000 0x00015000 0x001000>, /* ap 19 */
1031 <0x0003c000 0x0003c000 0x002000>, /* ap 20 */
1032 <0x0003e000 0x0003e000 0x001000>, /* ap 21 */
1033 <0x00040000 0x00040000 0x001000>, /* ap 22 */
1034 <0x00041000 0x00041000 0x001000>, /* ap 23 */
1035 <0x00042000 0x00042000 0x001000>, /* ap 24 */
1036 <0x00043000 0x00043000 0x001000>, /* ap 25 */
1037 <0x00044000 0x00044000 0x001000>, /* ap 26 */
1038 <0x00045000 0x00045000 0x001000>, /* ap 27 */
1039 <0x00046000 0x00046000 0x001000>, /* ap 28 */
1040 <0x00047000 0x00047000 0x001000>, /* ap 29 */
1041 <0x00048000 0x00048000 0x001000>, /* ap 30 */
1042 <0x00049000 0x00049000 0x001000>, /* ap 31 */
1043 <0x0004c000 0x0004c000 0x001000>, /* ap 32 */
1044 <0x0004d000 0x0004d000 0x001000>, /* ap 33 */
1045 <0x00050000 0x00050000 0x002000>, /* ap 34 */
1046 <0x00052000 0x00052000 0x001000>, /* ap 35 */
1047 <0x00060000 0x00060000 0x001000>, /* ap 36 */
1048 <0x00061000 0x00061000 0x001000>, /* ap 37 */
1049 <0x00080000 0x00080000 0x010000>, /* ap 38 */
1050 <0x00090000 0x00090000 0x001000>, /* ap 39 */
1051 <0x000a0000 0x000a0000 0x010000>, /* ap 40 */
1052 <0x000b0000 0x000b0000 0x001000>, /* ap 41 */
1053 <0x00030000 0x00030000 0x001000>, /* ap 77 */
1054 <0x00031000 0x00031000 0x001000>, /* ap 78 */
1055 <0x0004a000 0x0004a000 0x001000>, /* ap 85 */
1056 <0x0004b000 0x0004b000 0x001000>, /* ap 86 */
1057 <0x000c8000 0x000c8000 0x001000>, /* ap 87 */
1058 <0x000c9000 0x000c9000 0x001000>, /* ap 88 */
1059 <0x000cc000 0x000cc000 0x001000>, /* ap 89 */
1060 <0x000cd000 0x000cd000 0x001000>, /* ap 90 */
1061 <0x000ca000 0x000ca000 0x001000>, /* ap 91 */
1062 <0x000cb000 0x000cb000 0x001000>, /* ap 92 */
1063 <0x46000000 0x46000000 0x400000>, /* l3 data port */
1064 <0x46400000 0x46400000 0x400000>; /* l3 data port */
1066 target-module@8000 { /* 0x48008000, ap 6 10.0 */
1071 ranges = <0x0 0x8000 0x1000>;
1074 target-module@14000 { /* 0x48014000, ap 18 58.0 */
1079 ranges = <0x0 0x14000 0x1000>;
1082 target-module@16000 { /* 0x48016000, ap 8 3c.0 */
1087 ranges = <0x0 0x16000 0x1000>;
1090 target-module@22000 { /* 0x48022000, ap 10 12.0 */
1092 reg = <0x22050 0x4>,
1093 <0x22054 0x4>,
1094 <0x22058 0x4>;
1104 clocks = <&l4ls_clkctrl AM3_L4LS_UART2_CLKCTRL 0>;
1108 ranges = <0x0 0x22000 0x1000>;
1110 uart1: serial@0 {
1113 reg = <0x0 0x1000>;
1116 dmas = <&edma 28 0>, <&edma 29 0>;
1121 target-module@24000 { /* 0x48024000, ap 12 14.0 */
1123 reg = <0x24050 0x4>,
1124 <0x24054 0x4>,
1125 <0x24058 0x4>;
1135 clocks = <&l4ls_clkctrl AM3_L4LS_UART3_CLKCTRL 0>;
1139 ranges = <0x0 0x24000 0x1000>;
1141 uart2: serial@0 {
1144 reg = <0x0 0x1000>;
1147 dmas = <&edma 30 0>, <&edma 31 0>;
1152 target-module@2a000 { /* 0x4802a000, ap 14 2a.0 */
1154 reg = <0x2a000 0x8>,
1155 <0x2a010 0x8>,
1156 <0x2a090 0x8>;
1168 clocks = <&l4ls_clkctrl AM3_L4LS_I2C2_CLKCTRL 0>;
1172 ranges = <0x0 0x2a000 0x1000>;
1174 i2c1: i2c@0 {
1177 #size-cells = <0>;
1178 reg = <0x0 0x1000>;
1184 target-module@30000 { /* 0x48030000, ap 77 08.0 */
1186 reg = <0x30000 0x4>,
1187 <0x30110 0x4>,
1188 <0x30114 0x4>;
1198 clocks = <&l4ls_clkctrl AM3_L4LS_SPI0_CLKCTRL 0>;
1202 ranges = <0x0 0x30000 0x1000>;
1204 spi0: spi@0 {
1207 #size-cells = <0>;
1208 reg = <0x0 0x400>;
1211 dmas = <&edma 16 0
1212 &edma 17 0
1213 &edma 18 0
1214 &edma 19 0>;
1220 target-module@38000 { /* 0x48038000, ap 16 02.0 */
1222 reg = <0x38000 0x4>,
1223 <0x38004 0x4>;
1229 clocks = <&l3s_clkctrl AM3_L3S_MCASP0_CLKCTRL 0>;
1233 ranges = <0x0 0x38000 0x2000>,
1234 <0x46000000 0x46000000 0x400000>;
1236 mcasp0: mcasp@0 {
1238 reg = <0x0 0x2000>,
1239 <0x46000000 0x400000>;
1250 target-module@3c000 { /* 0x4803c000, ap 20 32.0 */
1252 reg = <0x3c000 0x4>,
1253 <0x3c004 0x4>;
1259 clocks = <&l3s_clkctrl AM3_L3S_MCASP1_CLKCTRL 0>;
1263 ranges = <0x0 0x3c000 0x2000>,
1264 <0x46400000 0x46400000 0x400000>;
1266 mcasp1: mcasp@0 {
1268 reg = <0x0 0x2000>,
1269 <0x46400000 0x400000>;
1280 timer2_target: target-module@40000 { /* 0x48040000, ap 22 1e.0 */
1282 reg = <0x40000 0x4>,
1283 <0x40010 0x4>,
1284 <0x40014 0x4>;
1292 clocks = <&l4ls_clkctrl AM3_L4LS_TIMER2_CLKCTRL 0>;
1296 ranges = <0x0 0x40000 0x1000>;
1298 timer2: timer@0 {
1300 reg = <0x0 0x400>;
1307 target-module@42000 { /* 0x48042000, ap 24 1c.0 */
1309 reg = <0x42000 0x4>,
1310 <0x42010 0x4>,
1311 <0x42014 0x4>;
1319 clocks = <&l4ls_clkctrl AM3_L4LS_TIMER3_CLKCTRL 0>;
1323 ranges = <0x0 0x42000 0x1000>;
1325 timer3: timer@0 {
1327 reg = <0x0 0x400>;
1334 target-module@44000 { /* 0x48044000, ap 26 26.0 */
1336 reg = <0x44000 0x4>,
1337 <0x44010 0x4>,
1338 <0x44014 0x4>;
1346 clocks = <&l4ls_clkctrl AM3_L4LS_TIMER4_CLKCTRL 0>;
1350 ranges = <0x0 0x44000 0x1000>;
1352 timer4: timer@0 {
1354 reg = <0x0 0x400>;
1362 target-module@46000 { /* 0x48046000, ap 28 28.0 */
1364 reg = <0x46000 0x4>,
1365 <0x46010 0x4>,
1366 <0x46014 0x4>;
1374 clocks = <&l4ls_clkctrl AM3_L4LS_TIMER5_CLKCTRL 0>;
1378 ranges = <0x0 0x46000 0x1000>;
1380 timer5: timer@0 {
1382 reg = <0x0 0x400>;
1390 target-module@48000 { /* 0x48048000, ap 30 22.0 */
1392 reg = <0x48000 0x4>,
1393 <0x48010 0x4>,
1394 <0x48014 0x4>;
1402 clocks = <&l4ls_clkctrl AM3_L4LS_TIMER6_CLKCTRL 0>;
1406 ranges = <0x0 0x48000 0x1000>;
1408 timer6: timer@0 {
1410 reg = <0x0 0x400>;
1418 target-module@4a000 { /* 0x4804a000, ap 85 60.0 */
1420 reg = <0x4a000 0x4>,
1421 <0x4a010 0x4>,
1422 <0x4a014 0x4>;
1430 clocks = <&l4ls_clkctrl AM3_L4LS_TIMER7_CLKCTRL 0>;
1434 ranges = <0x0 0x4a000 0x1000>;
1436 timer7: timer@0 {
1438 reg = <0x0 0x400>;
1446 target-module@4c000 { /* 0x4804c000, ap 32 36.0 */
1448 reg = <0x4c000 0x4>,
1449 <0x4c010 0x4>,
1450 <0x4c114 0x4>;
1461 clocks = <&l4ls_clkctrl AM3_L4LS_GPIO2_CLKCTRL 0>,
1466 ranges = <0x0 0x4c000 0x1000>;
1468 gpio1: gpio@0 {
1470 gpio-ranges = <&am33xx_pinmux 0 0 8>,
1478 reg = <0x0 0x1000>;
1483 target-module@50000 { /* 0x48050000, ap 34 2c.0 */
1488 ranges = <0x0 0x50000 0x2000>;
1491 target-module@60000 { /* 0x48060000, ap 36 0c.0 */
1493 reg = <0x602fc 0x4>,
1494 <0x60110 0x4>,
1495 <0x60114 0x4>;
1506 clocks = <&l4ls_clkctrl AM3_L4LS_MMC1_CLKCTRL 0>;
1510 ranges = <0x0 0x60000 0x1000>;
1512 mmc1: mmc@0 {
1515 dmas = <&edma 24 0>, <&edma 25 0>;
1518 reg = <0x0 0x1000>;
1523 target-module@80000 { /* 0x48080000, ap 38 18.0 */
1525 reg = <0x80000 0x4>,
1526 <0x80010 0x4>,
1527 <0x80014 0x4>;
1537 clocks = <&l4ls_clkctrl AM3_L4LS_ELM_CLKCTRL 0>;
1541 ranges = <0x0 0x80000 0x10000>;
1543 elm: elm@0 {
1545 reg = <0x0 0x2000>;
1551 target-module@a0000 { /* 0x480a0000, ap 40 5e.0 */
1556 ranges = <0x0 0xa0000 0x10000>;
1559 target-module@c8000 { /* 0x480c8000, ap 87 06.0 */
1561 reg = <0xc8000 0x4>,
1562 <0xc8010 0x4>;
1569 clocks = <&l4ls_clkctrl AM3_L4LS_MAILBOX_CLKCTRL 0>;
1573 ranges = <0x0 0xc8000 0x1000>;
1575 mailbox: mailbox@0 {
1577 reg = <0x0 0x200>;
1584 ti,mbox-tx = <0 0 0>;
1585 ti,mbox-rx = <0 0 3>;
1590 target-module@ca000 { /* 0x480ca000, ap 91 40.0 */
1592 reg = <0xca000 0x4>,
1593 <0xca010 0x4>,
1594 <0xca014 0x4>;
1605 clocks = <&l4ls_clkctrl AM3_L4LS_SPINLOCK_CLKCTRL 0>;
1609 ranges = <0x0 0xca000 0x1000>;
1611 hwspinlock: spinlock@0 {
1613 reg = <0x0 0x1000>;
1618 target-module@cc000 { /* 0x480cc000, ap 89 0e.0 */
1623 ranges = <0x0 0xcc000 0x1000>;
1627 segment@100000 { /* 0x48100000 */
1631 ranges = <0x0008c000 0x0018c000 0x001000>, /* ap 42 */
1632 <0x0008d000 0x0018d000 0x001000>, /* ap 43 */
1633 <0x0008e000 0x0018e000 0x001000>, /* ap 44 */
1634 <0x0008f000 0x0018f000 0x001000>, /* ap 45 */
1635 <0x0009c000 0x0019c000 0x001000>, /* ap 46 */
1636 <0x0009d000 0x0019d000 0x001000>, /* ap 47 */
1637 <0x000a6000 0x001a6000 0x001000>, /* ap 48 */
1638 <0x000a7000 0x001a7000 0x001000>, /* ap 49 */
1639 <0x000a8000 0x001a8000 0x001000>, /* ap 50 */
1640 <0x000a9000 0x001a9000 0x001000>, /* ap 51 */
1641 <0x000aa000 0x001aa000 0x001000>, /* ap 52 */
1642 <0x000ab000 0x001ab000 0x001000>, /* ap 53 */
1643 <0x000ac000 0x001ac000 0x001000>, /* ap 54 */
1644 <0x000ad000 0x001ad000 0x001000>, /* ap 55 */
1645 <0x000ae000 0x001ae000 0x001000>, /* ap 56 */
1646 <0x000af000 0x001af000 0x001000>, /* ap 57 */
1647 <0x000b0000 0x001b0000 0x010000>, /* ap 58 */
1648 <0x000c0000 0x001c0000 0x001000>, /* ap 59 */
1649 <0x000cc000 0x001cc000 0x002000>, /* ap 60 */
1650 <0x000ce000 0x001ce000 0x002000>, /* ap 61 */
1651 <0x000d0000 0x001d0000 0x002000>, /* ap 62 */
1652 <0x000d2000 0x001d2000 0x002000>, /* ap 63 */
1653 <0x000d8000 0x001d8000 0x001000>, /* ap 64 */
1654 <0x000d9000 0x001d9000 0x001000>, /* ap 65 */
1655 <0x000a0000 0x001a0000 0x001000>, /* ap 79 */
1656 <0x000a1000 0x001a1000 0x001000>, /* ap 80 */
1657 <0x000a2000 0x001a2000 0x001000>, /* ap 81 */
1658 <0x000a3000 0x001a3000 0x001000>, /* ap 82 */
1659 <0x000a4000 0x001a4000 0x001000>, /* ap 83 */
1660 <0x000a5000 0x001a5000 0x001000>; /* ap 84 */
1662 target-module@8c000 { /* 0x4818c000, ap 42 04.0 */
1667 ranges = <0x0 0x8c000 0x1000>;
1670 target-module@8e000 { /* 0x4818e000, ap 44 0a.0 */
1675 ranges = <0x0 0x8e000 0x1000>;
1678 target-module@9c000 { /* 0x4819c000, ap 46 5a.0 */
1680 reg = <0x9c000 0x8>,
1681 <0x9c010 0x8>,
1682 <0x9c090 0x8>;
1694 clocks = <&l4ls_clkctrl AM3_L4LS_I2C3_CLKCTRL 0>;
1698 ranges = <0x0 0x9c000 0x1000>;
1700 i2c2: i2c@0 {
1703 #size-cells = <0>;
1704 reg = <0x0 0x1000>;
1710 target-module@a0000 { /* 0x481a0000, ap 79 24.0 */
1712 reg = <0xa0000 0x4>,
1713 <0xa0110 0x4>,
1714 <0xa0114 0x4>;
1724 clocks = <&l4ls_clkctrl AM3_L4LS_SPI1_CLKCTRL 0>;
1728 ranges = <0x0 0xa0000 0x1000>;
1730 spi1: spi@0 {
1733 #size-cells = <0>;
1734 reg = <0x0 0x400>;
1737 dmas = <&edma 42 0
1738 &edma 43 0
1739 &edma 44 0
1740 &edma 45 0>;
1746 target-module@a2000 { /* 0x481a2000, ap 81 2e.0 */
1751 ranges = <0x0 0xa2000 0x1000>;
1754 target-module@a4000 { /* 0x481a4000, ap 83 30.0 */
1759 ranges = <0x0 0xa4000 0x1000>;
1762 target-module@a6000 { /* 0x481a6000, ap 48 16.0 */
1764 reg = <0xa6050 0x4>,
1765 <0xa6054 0x4>,
1766 <0xa6058 0x4>;
1776 clocks = <&l4ls_clkctrl AM3_L4LS_UART4_CLKCTRL 0>;
1780 ranges = <0x0 0xa6000 0x1000>;
1782 uart3: serial@0 {
1785 reg = <0x0 0x1000>;
1791 target-module@a8000 { /* 0x481a8000, ap 50 20.0 */
1793 reg = <0xa8050 0x4>,
1794 <0xa8054 0x4>,
1795 <0xa8058 0x4>;
1805 clocks = <&l4ls_clkctrl AM3_L4LS_UART5_CLKCTRL 0>;
1809 ranges = <0x0 0xa8000 0x1000>;
1811 uart4: serial@0 {
1814 reg = <0x0 0x1000>;
1820 target-module@aa000 { /* 0x481aa000, ap 52 1a.0 */
1822 reg = <0xaa050 0x4>,
1823 <0xaa054 0x4>,
1824 <0xaa058 0x4>;
1834 clocks = <&l4ls_clkctrl AM3_L4LS_UART6_CLKCTRL 0>;
1838 ranges = <0x0 0xaa000 0x1000>;
1840 uart5: serial@0 {
1843 reg = <0x0 0x1000>;
1849 target-module@ac000 { /* 0x481ac000, ap 54 38.0 */
1851 reg = <0xac000 0x4>,
1852 <0xac010 0x4>,
1853 <0xac114 0x4>;
1864 clocks = <&l4ls_clkctrl AM3_L4LS_GPIO3_CLKCTRL 0>,
1869 ranges = <0x0 0xac000 0x1000>;
1871 gpio2: gpio@0 {
1873 gpio-ranges = <&am33xx_pinmux 0 34 18>,
1880 reg = <0x0 0x1000>;
1885 gpio3_target: target-module@ae000 { /* 0x481ae000, ap 56 3a.0 */
1887 reg = <0xae000 0x4>,
1888 <0xae010 0x4>,
1889 <0xae114 0x4>;
1900 clocks = <&l4ls_clkctrl AM3_L4LS_GPIO4_CLKCTRL 0>,
1905 ranges = <0x0 0xae000 0x1000>;
1907 gpio3: gpio@0 {
1909 gpio-ranges = <&am33xx_pinmux 0 66 5>,
1918 reg = <0x0 0x1000>;
1923 target-module@b0000 { /* 0x481b0000, ap 58 50.0 */
1928 ranges = <0x0 0xb0000 0x10000>;
1931 target-module@cc000 { /* 0x481cc000, ap 60 46.0 */
1933 reg = <0xcc020 0x4>;
1936 clocks = <&l4ls_clkctrl AM3_L4LS_D_CAN0_CLKCTRL 0>,
1941 ranges = <0x0 0xcc000 0x2000>;
1943 dcan0: can@0 {
1945 reg = <0x0 0x2000>;
1948 syscon-raminit = <&scm_conf 0x644 0>;
1954 target-module@d0000 { /* 0x481d0000, ap 62 42.0 */
1956 reg = <0xd0020 0x4>;
1959 clocks = <&l4ls_clkctrl AM3_L4LS_D_CAN1_CLKCTRL 0>,
1964 ranges = <0x0 0xd0000 0x2000>;
1966 dcan1: can@0 {
1968 reg = <0x0 0x2000>;
1971 syscon-raminit = <&scm_conf 0x644 1>;
1977 target-module@d8000 { /* 0x481d8000, ap 64 66.0 */
1979 reg = <0xd82fc 0x4>,
1980 <0xd8110 0x4>,
1981 <0xd8114 0x4>;
1992 clocks = <&l4ls_clkctrl AM3_L4LS_MMC2_CLKCTRL 0>;
1996 ranges = <0x0 0xd8000 0x1000>;
1998 mmc2: mmc@0 {
2001 dmas = <&edma 2 0
2002 &edma 3 0>;
2005 reg = <0x0 0x1000>;
2011 segment@200000 { /* 0x48200000 */
2015 ranges = <0x00000000 0x00200000 0x010000>;
2017 target-module@0 {
2020 clocks = <&mpu_clkctrl AM3_MPU_MPU_CLKCTRL 0>;
2025 ranges = <0 0 0x10000>;
2027 mpu@0 {
2035 segment@300000 { /* 0x48300000 */
2039 ranges = <0x00000000 0x00300000 0x001000>, /* ap 66 */
2040 <0x00001000 0x00301000 0x001000>, /* ap 67 */
2041 <0x00002000 0x00302000 0x001000>, /* ap 68 */
2042 <0x00003000 0x00303000 0x001000>, /* ap 69 */
2043 <0x00004000 0x00304000 0x001000>, /* ap 70 */
2044 <0x00005000 0x00305000 0x001000>, /* ap 71 */
2045 <0x0000e000 0x0030e000 0x001000>, /* ap 72 */
2046 <0x0000f000 0x0030f000 0x001000>, /* ap 73 */
2047 <0x00018000 0x00318000 0x004000>, /* ap 74 */
2048 <0x0001c000 0x0031c000 0x001000>, /* ap 75 */
2049 <0x00010000 0x00310000 0x002000>, /* ap 76 */
2050 <0x00012000 0x00312000 0x001000>, /* ap 93 */
2051 <0x00015000 0x00315000 0x001000>, /* ap 94 */
2052 <0x00016000 0x00316000 0x001000>, /* ap 95 */
2053 <0x00017000 0x00317000 0x001000>, /* ap 96 */
2054 <0x00013000 0x00313000 0x001000>, /* ap 97 */
2055 <0x00014000 0x00314000 0x001000>, /* ap 98 */
2056 <0x00020000 0x00320000 0x001000>, /* ap 99 */
2057 <0x00021000 0x00321000 0x001000>, /* ap 100 */
2058 <0x00022000 0x00322000 0x001000>, /* ap 101 */
2059 <0x00023000 0x00323000 0x001000>, /* ap 102 */
2060 <0x00024000 0x00324000 0x001000>, /* ap 103 */
2061 <0x00025000 0x00325000 0x001000>; /* ap 104 */
2063 target-module@0 { /* 0x48300000, ap 66 48.0 */
2065 reg = <0x0 0x4>,
2066 <0x4 0x4>;
2077 clocks = <&l4ls_clkctrl AM3_L4LS_EPWMSS0_CLKCTRL 0>;
2081 ranges = <0x0 0x0 0x1000>;
2083 epwmss0: epwmss@0 {
2085 reg = <0x0 0x10>;
2089 ranges = <0 0 0x1000>;
2094 reg = <0x100 0x80>;
2102 reg = <0x180 0x80>;
2112 reg = <0x200 0x80>;
2120 target-module@2000 { /* 0x48302000, ap 68 52.0 */
2122 reg = <0x2000 0x4>,
2123 <0x2004 0x4>;
2134 clocks = <&l4ls_clkctrl AM3_L4LS_EPWMSS1_CLKCTRL 0>;
2138 ranges = <0x0 0x2000 0x1000>;
2140 epwmss1: epwmss@0 {
2142 reg = <0x0 0x10>;
2146 ranges = <0 0 0x1000>;
2151 reg = <0x100 0x80>;
2159 reg = <0x180 0x80>;
2169 reg = <0x200 0x80>;
2177 target-module@4000 { /* 0x48304000, ap 70 44.0 */
2179 reg = <0x4000 0x4>,
2180 <0x4004 0x4>;
2191 clocks = <&l4ls_clkctrl AM3_L4LS_EPWMSS2_CLKCTRL 0>;
2195 ranges = <0x0 0x4000 0x1000>;
2197 epwmss2: epwmss@0 {
2199 reg = <0x0 0x10>;
2203 ranges = <0 0 0x1000>;
2208 reg = <0x100 0x80>;
2216 reg = <0x180 0x80>;
2226 reg = <0x200 0x80>;
2234 target-module@e000 { /* 0x4830e000, ap 72 4a.0 */
2236 reg = <0xe000 0x4>,
2237 <0xe054 0x4>;
2246 clocks = <&lcdc_clkctrl AM3_LCDC_LCDC_CLKCTRL 0>;
2250 ranges = <0x0 0xe000 0x1000>;
2252 lcdc: lcdc@0 {
2254 reg = <0x0 0x1000>;
2260 target-module@10000 { /* 0x48310000, ap 76 4e.1 */
2262 reg = <0x11fe0 0x4>,
2263 <0x11fe4 0x4>;
2269 clocks = <&l4ls_clkctrl AM3_L4LS_RNG_CLKCTRL 0>;
2273 ranges = <0x0 0x10000 0x2000>;
2275 rng: rng@0 {
2277 reg = <0x0 0x2000>;
2282 target-module@13000 { /* 0x48313000, ap 97 62.0 */
2287 ranges = <0x0 0x13000 0x1000>;
2290 target-module@15000 { /* 0x48315000, ap 94 56.0 */
2295 ranges = <0x00000000 0x00015000 0x00001000>,
2296 <0x00001000 0x00016000 0x00001000>;
2299 target-module@18000 { /* 0x48318000, ap 74 4c.0 */
2304 ranges = <0x0 0x18000 0x4000>;
2307 target-module@20000 { /* 0x48320000, ap 99 34.0 */
2312 ranges = <0x0 0x20000 0x1000>;
2315 target-module@22000 { /* 0x48322000, ap 101 3e.0 */
2320 ranges = <0x0 0x22000 0x1000>;
2323 target-module@24000 { /* 0x48324000, ap 103 68.0 */
2328 ranges = <0x0 0x24000 0x1000>;