Lines Matching +full:stm32 +full:- +full:dma2d
2 * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
4 * This file is dual-licensed: you can use it either under the terms
22 * MA 02110-1301 USA
48 #include "../armv7-m.dtsi"
49 #include <dt-bindings/clock/stm32fx-clock.h>
50 #include <dt-bindings/mfd/stm32f4-rcc.h>
53 #address-cells = <1>;
54 #size-cells = <1>;
57 clk_hse: clk-hse {
58 #clock-cells = <0>;
59 compatible = "fixed-clock";
60 clock-frequency = <0>;
63 clk_lse: clk-lse {
64 #clock-cells = <0>;
65 compatible = "fixed-clock";
66 clock-frequency = <32768>;
69 clk_lsi: clk-lsi {
70 #clock-cells = <0>;
71 compatible = "fixed-clock";
72 clock-frequency = <32000>;
75 clk_i2s_ckin: i2s-ckin {
76 #clock-cells = <0>;
77 compatible = "fixed-clock";
78 clock-frequency = <0>;
84 compatible = "st,stm32f4-otp";
86 #address-cells = <1>;
87 #size-cells = <1>;
97 #address-cells = <1>;
98 #size-cells = <0>;
99 compatible = "st,stm32-timers";
102 clock-names = "int";
106 compatible = "st,stm32-pwm";
107 #pwm-cells = <3>;
112 compatible = "st,stm32-timer-trigger";
119 #address-cells = <1>;
120 #size-cells = <0>;
121 compatible = "st,stm32-timers";
124 clock-names = "int";
128 compatible = "st,stm32-pwm";
129 #pwm-cells = <3>;
134 compatible = "st,stm32-timer-trigger";
141 #address-cells = <1>;
142 #size-cells = <0>;
143 compatible = "st,stm32-timers";
146 clock-names = "int";
150 compatible = "st,stm32-pwm";
151 #pwm-cells = <3>;
156 compatible = "st,stm32-timer-trigger";
163 #address-cells = <1>;
164 #size-cells = <0>;
165 compatible = "st,stm32-timers";
168 clock-names = "int";
172 compatible = "st,stm32-pwm";
173 #pwm-cells = <3>;
178 compatible = "st,stm32-timer-trigger";
185 #address-cells = <1>;
186 #size-cells = <0>;
187 compatible = "st,stm32-timers";
190 clock-names = "int";
194 compatible = "st,stm32-timer-trigger";
201 #address-cells = <1>;
202 #size-cells = <0>;
203 compatible = "st,stm32-timers";
206 clock-names = "int";
210 compatible = "st,stm32-timer-trigger";
217 #address-cells = <1>;
218 #size-cells = <0>;
219 compatible = "st,stm32-timers";
222 clock-names = "int";
226 compatible = "st,stm32-pwm";
227 #pwm-cells = <3>;
232 compatible = "st,stm32-timer-trigger";
239 compatible = "st,stm32-timers";
242 clock-names = "int";
246 compatible = "st,stm32-pwm";
247 #pwm-cells = <3>;
253 compatible = "st,stm32-timers";
256 clock-names = "int";
260 compatible = "st,stm32-pwm";
261 #pwm-cells = <3>;
267 compatible = "st,stm32-rtc";
270 assigned-clocks = <&rcc 1 CLK_RTC>;
271 assigned-clock-parents = <&rcc 1 CLK_LSE>;
272 interrupt-parent = <&exti>;
279 compatible = "st,stm32-iwdg";
282 clock-names = "lsi";
287 #address-cells = <1>;
288 #size-cells = <0>;
289 compatible = "st,stm32f4-spi";
297 #address-cells = <1>;
298 #size-cells = <0>;
299 compatible = "st,stm32f4-spi";
307 compatible = "st,stm32-uart";
315 compatible = "st,stm32-uart";
322 dma-names = "rx", "tx";
326 compatible = "st,stm32-uart";
334 compatible = "st,stm32-uart";
342 compatible = "st,stm32f4-i2c";
348 #address-cells = <1>;
349 #size-cells = <0>;
354 compatible = "st,stm32f4-i2c";
360 #address-cells = <1>;
361 #size-cells = <0>;
366 compatible = "st,stm32f4-bxcan";
369 interrupt-names = "tx", "rx0", "rx1", "sce";
372 st,can-primary;
378 compatible = "st,stm32f4-gcan", "syscon";
384 compatible = "st,stm32f4-bxcan";
387 interrupt-names = "tx", "rx0", "rx1", "sce";
390 st,can-secondary;
396 compatible = "st,stm32f4-dac-core";
400 clock-names = "pclk";
401 #address-cells = <1>;
402 #size-cells = <0>;
406 compatible = "st,stm32-dac";
407 #io-channel-cells = <1>;
413 compatible = "st,stm32-dac";
414 #io-channel-cells = <1>;
421 compatible = "st,stm32-uart";
429 compatible = "st,stm32-uart";
437 #address-cells = <1>;
438 #size-cells = <0>;
439 compatible = "st,stm32-timers";
442 clock-names = "int";
446 compatible = "st,stm32-pwm";
447 #pwm-cells = <3>;
452 compatible = "st,stm32-timer-trigger";
459 #address-cells = <1>;
460 #size-cells = <0>;
461 compatible = "st,stm32-timers";
464 clock-names = "int";
468 compatible = "st,stm32-pwm";
469 #pwm-cells = <3>;
474 compatible = "st,stm32-timer-trigger";
481 compatible = "st,stm32-uart";
488 dma-names = "rx", "tx";
492 compatible = "st,stm32-uart";
500 compatible = "st,stm32f4-adc-core";
504 clock-names = "adc";
505 interrupt-controller;
506 #interrupt-cells = <1>;
507 #address-cells = <1>;
508 #size-cells = <0>;
512 compatible = "st,stm32f4-adc";
513 #io-channel-cells = <1>;
516 interrupt-parent = <&adc>;
519 dma-names = "rx";
524 compatible = "st,stm32f4-adc";
525 #io-channel-cells = <1>;
528 interrupt-parent = <&adc>;
531 dma-names = "rx";
536 compatible = "st,stm32f4-adc";
537 #io-channel-cells = <1>;
540 interrupt-parent = <&adc>;
543 dma-names = "rx";
550 arm,primecell-periphid = <0x00880180>;
553 clock-names = "apb_pclk";
555 max-frequency = <48000000>;
560 #address-cells = <1>;
561 #size-cells = <0>;
562 compatible = "st,stm32f4-spi";
570 #address-cells = <1>;
571 #size-cells = <0>;
572 compatible = "st,stm32f4-spi";
580 compatible = "st,stm32-syscfg", "syscon";
584 exti: interrupt-controller@40013c00 {
585 compatible = "st,stm32-exti";
586 interrupt-controller;
587 #interrupt-cells = <2>;
593 #address-cells = <1>;
594 #size-cells = <0>;
595 compatible = "st,stm32-timers";
598 clock-names = "int";
602 compatible = "st,stm32-pwm";
603 #pwm-cells = <3>;
608 compatible = "st,stm32-timer-trigger";
615 compatible = "st,stm32-timers";
618 clock-names = "int";
622 compatible = "st,stm32-pwm";
623 #pwm-cells = <3>;
629 compatible = "st,stm32-timers";
632 clock-names = "int";
636 compatible = "st,stm32-pwm";
637 #pwm-cells = <3>;
643 #address-cells = <1>;
644 #size-cells = <0>;
645 compatible = "st,stm32f4-spi";
651 dma-names = "rx", "tx";
656 #address-cells = <1>;
657 #size-cells = <0>;
658 compatible = "st,stm32f4-spi";
665 pwrcfg: power-config@40007000 {
666 compatible = "st,stm32-power-config", "syscon";
670 ltdc: display-controller@40016800 {
671 compatible = "st,stm32-ltdc";
676 clock-names = "lcd";
681 compatible = "st,stm32f4-crc";
688 #reset-cells = <1>;
689 #clock-cells = <2>;
690 compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
694 assigned-clocks = <&rcc 1 CLK_HSE_RTC>;
695 assigned-clock-rates = <1000000>;
698 dma1: dma-controller@40026000 {
699 compatible = "st,stm32-dma";
710 #dma-cells = <4>;
713 dma2: dma-controller@40026400 {
714 compatible = "st,stm32-dma";
725 #dma-cells = <4>;
730 compatible = "st,stm32-dwmac", "snps,dwmac-3.50a";
732 reg-names = "stmmaceth";
734 interrupt-names = "macirq";
735 clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx";
741 snps,mixed-burst;
745 dma2d: dma2d@4002b000 { label
746 compatible = "st,stm32-dma2d";
749 resets = <&rcc STM32F4_AHB1_RESET(DMA2D)>;
750 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA2D)>;
751 clock-names = "dma2d";
760 clock-names = "otg";
765 compatible = "st,stm32f4x9-fsotg";
769 clock-names = "otg";
774 compatible = "st,stm32-dcmi";
779 clock-names = "mclk";
780 pinctrl-names = "default";
781 pinctrl-0 = <&dcmi_pins>;
783 dma-names = "tx";
788 compatible = "st,stm32-rng";