Lines Matching +full:pll1 +full:- +full:div2
1 // SPDX-License-Identifier: GPL-2.0-only
5 #include <dt-bindings/clock/stih410-clks.h>
10 clk_sysin: clk-sysin {
11 #clock-cells = <0>;
12 compatible = "fixed-clock";
13 clock-frequency = <30000000>;
14 clock-output-names = "CLK_SYSIN";
17 clk_tmdsout_hdmi: clk-tmdsout-hdmi {
18 #clock-cells = <0>;
19 compatible = "fixed-clock";
20 clock-frequency = <0>;
24 #address-cells = <1>;
25 #size-cells = <1>;
28 compatible = "st,stih410-clk", "simple-bus";
33 clockgen-a9@92b0000 {
34 compatible = "st,clkgen-c32";
37 clockgen_a9_pll: clockgen-a9-pll {
38 #clock-cells = <1>;
39 compatible = "st,stih407-clkgen-plla9";
47 clk_m_a9: clk-m-a9 {
48 #clock-cells = <0>;
49 compatible = "st,stih407-clkgen-a9-mux", "st,clkgen-mux";
59 arm_periph_clk: clk-m-a9-periphs {
60 #clock-cells = <0>;
61 compatible = "fixed-factor-clock";
63 clock-div = <2>;
64 clock-mult = <1>;
69 clockgen-a@90ff000 {
70 compatible = "st,clkgen-c32";
73 clk_s_a0_pll: clk-s-a0-pll {
74 #clock-cells = <1>;
75 compatible = "st,clkgen-pll0-a0";
80 clk_s_a0_flexgen: clk-s-a0-flexgen {
81 compatible = "st,flexgen", "st,flexgen-stih410-a0";
83 #clock-cells = <1>;
90 clk_s_c0: clockgen-c@9103000 {
91 compatible = "st,clkgen-c32";
94 clk_s_c0_pll0: clk-s-c0-pll0 {
95 #clock-cells = <1>;
96 compatible = "st,clkgen-pll0-c0";
101 clk_s_c0_pll1: clk-s-c0-pll1 {
102 #clock-cells = <1>;
103 compatible = "st,clkgen-pll1-c0";
108 clk_s_c0_quadfs: clk-s-c0-quadfs {
109 #clock-cells = <1>;
110 compatible = "st,quadfs-pll";
115 clk_s_c0_flexgen: clk-s-c0-flexgen {
116 #clock-cells = <1>;
117 compatible = "st,flexgen", "st,flexgen-stih410-c0";
130 clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s {
131 #clock-cells = <0>;
132 compatible = "fixed-factor-clock";
136 clock-output-names = "clk-m-a9-ext2f-div2";
138 clock-div = <2>;
139 clock-mult = <1>;
144 clockgen-d0@9104000 {
145 compatible = "st,clkgen-c32";
148 clk_s_d0_quadfs: clk-s-d0-quadfs {
149 #clock-cells = <1>;
150 compatible = "st,quadfs-d0";
155 clk_s_d0_flexgen: clk-s-d0-flexgen {
156 #clock-cells = <1>;
157 compatible = "st,flexgen", "st,flexgen-stih410-d0";
167 clockgen-d2@9106000 {
168 compatible = "st,clkgen-c32";
171 clk_s_d2_quadfs: clk-s-d2-quadfs {
172 #clock-cells = <1>;
173 compatible = "st,quadfs-d2";
178 clk_s_d2_flexgen: clk-s-d2-flexgen {
179 #clock-cells = <1>;
180 compatible = "st,flexgen", "st,flexgen-stih407-d2";
192 clockgen-d3@9107000 {
193 compatible = "st,clkgen-c32";
196 clk_s_d3_quadfs: clk-s-d3-quadfs {
197 #clock-cells = <1>;
198 compatible = "st,quadfs-d3";
203 clk_s_d3_flexgen: clk-s-d3-flexgen {
204 #clock-cells = <1>;
205 compatible = "st,flexgen", "st,flexgen-stih407-d3";