Lines Matching +full:pll1 +full:- +full:div2
1 // SPDX-License-Identifier: GPL-2.0-only
5 #include <dt-bindings/clock/stih407-clks.h>
10 clk_sysin: clk-sysin {
11 #clock-cells = <0>;
12 compatible = "fixed-clock";
13 clock-frequency = <30000000>;
16 clk_tmdsout_hdmi: clk-tmdsout-hdmi {
17 #clock-cells = <0>;
18 compatible = "fixed-clock";
19 clock-frequency = <0>;
23 #address-cells = <1>;
24 #size-cells = <1>;
30 clockgen-a9@92b0000 {
31 compatible = "st,clkgen-c32";
34 clockgen_a9_pll: clockgen-a9-pll {
35 #clock-cells = <1>;
36 compatible = "st,stih407-clkgen-plla9";
41 clk_m_a9: clk-m-a9 {
42 #clock-cells = <0>;
43 compatible = "st,stih407-clkgen-a9-mux";
53 arm_periph_clk: clk-m-a9-periphs {
54 #clock-cells = <0>;
55 compatible = "fixed-factor-clock";
58 clock-div = <2>;
59 clock-mult = <1>;
64 clockgen-a@90ff000 {
65 compatible = "st,clkgen-c32";
68 clk_s_a0_pll: clk-s-a0-pll {
69 #clock-cells = <1>;
70 compatible = "st,clkgen-pll0-a0";
75 clk_s_a0_flexgen: clk-s-a0-flexgen {
76 compatible = "st,flexgen", "st,flexgen-stih407-a0";
78 #clock-cells = <1>;
85 clk_s_c0: clockgen-c@9103000 {
86 compatible = "st,clkgen-c32";
89 clk_s_c0_pll0: clk-s-c0-pll0 {
90 #clock-cells = <1>;
91 compatible = "st,clkgen-pll0-c0";
96 clk_s_c0_pll1: clk-s-c0-pll1 {
97 #clock-cells = <1>;
98 compatible = "st,clkgen-pll1-c0";
103 clk_s_c0_quadfs: clk-s-c0-quadfs {
104 #clock-cells = <1>;
105 compatible = "st,quadfs-pll";
110 clk_s_c0_flexgen: clk-s-c0-flexgen {
111 #clock-cells = <1>;
112 compatible = "st,flexgen", "st,flexgen-stih407-c0";
125 clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s {
126 #clock-cells = <0>;
127 compatible = "fixed-factor-clock";
131 clock-output-names = "clk-m-a9-ext2f-div2";
133 clock-div = <2>;
134 clock-mult = <1>;
139 clockgen-d0@9104000 {
140 compatible = "st,clkgen-c32";
143 clk_s_d0_quadfs: clk-s-d0-quadfs {
144 #clock-cells = <1>;
145 compatible = "st,quadfs-d0";
150 clk_s_d0_flexgen: clk-s-d0-flexgen {
151 #clock-cells = <1>;
152 compatible = "st,flexgen", "st,flexgen-stih407-d0";
162 clockgen-d2@9106000 {
163 compatible = "st,clkgen-c32";
166 clk_s_d2_quadfs: clk-s-d2-quadfs {
167 #clock-cells = <1>;
168 compatible = "st,quadfs-d2";
173 clk_s_d2_flexgen: clk-s-d2-flexgen {
174 #clock-cells = <1>;
175 compatible = "st,flexgen", "st,flexgen-stih407-d2";
187 clockgen-d3@9107000 {
188 compatible = "st,clkgen-c32";
191 clk_s_d3_quadfs: clk-s-d3-quadfs {
192 #clock-cells = <1>;
193 compatible = "st,quadfs-d3";
198 clk_s_d3_flexgen: clk-s-d3-flexgen {
199 #clock-cells = <1>;
200 compatible = "st,flexgen", "st,flexgen-stih407-d3";