Lines Matching +full:1 +full:st

12 	model = "ST SPEAr1310 Evaluation Board";
13 compatible = "st,spear1310-evb", "st,spear1310";
14 #address-cells = <1>;
15 #size-cells = <1>;
28 st,pins = "i2c0_grp";
29 st,function = "i2c0";
32 st,pins = "i2s0_grp";
33 st,function = "i2s0";
36 st,pins = "i2s1_grp";
37 st,function = "i2s1";
40 st,pins = "arm_gpio_grp";
41 st,function = "arm_gpio";
44 st,pins = "clcd_grp" , "clcd_high_res";
45 st,function = "clcd";
48 st,pins = "gmii_grp";
49 st,function = "gmii";
52 st,pins = "ssp0_grp";
53 st,function = "ssp0";
56 st,pins = "keyboard_6x6_grp";
57 st,function = "keyboard";
60 st,pins = "sdhci_grp";
61 st,function = "sdhci";
64 st,pins = "smi_2_chips_grp";
65 st,function = "smi";
68 st,pins = "uart0_grp";
69 st,function = "uart0";
72 st,pins = "rs485_0_1_tdm_0_1_grp";
73 st,function = "rs485_0_1_tdm_0_1";
76 st,pins = "i2c_1_2_grp";
77 st,function = "i2c_1_2";
80 st,pins = "smii_0_1_2_grp";
81 st,function = "smii_0_1_2";
84 st,pins = "nand_8bit_grp",
86 st,function = "nand";
89 st,pins = "sata0_grp";
90 st,function = "sata";
93 st,pins = "pcie1_grp", "pcie2_grp";
94 st,function = "pci_express";
130 partition@1C0000 {
150 #address-cells = <1>;
153 button@1 {
176 #address-cells = <1>;
177 #size-cells = <1>;
179 st,smi-fast-mode;
328 st,mode = <0>;
346 cs-gpios = <&gpio1 7 0>, <&spics 0 0>, <&spics 1 0>;
349 compatible = "st,stmpe610";
351 #address-cells = <1>;
368 compatible = "st,stmpe-ts";
370 ts,mod-12b = <1>;
372 ts,adc-freq = <1>;
373 ts,ave-ctrl = <1>;
377 ts,i-drive = <1>;
381 flash@1 {
382 compatible = "st,m25p80";
383 reg = <1>;