Lines Matching +full:0 +full:x66038000
17 #size-cells = <0>;
19 cpu@0 {
22 reg = <0>;
118 #clock-cells = <0>;
123 #clock-cells = <0>;
138 reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
139 <0x506c0000 0x400>;
152 reg = <0x500c8000 0x2000>, <0x503c8100 0x8>,
153 <0x506c8000 0x400>;
166 reg = <0x54006000 0x100>;
168 #size-cells = <0>;
171 pinctrl-0 = <&pinctrl_spi0>;
179 reg = <0x54006100 0x100>;
181 #size-cells = <0>;
184 pinctrl-0 = <&pinctrl_spi1>;
192 reg = <0x54006800 0x40>;
195 pinctrl-0 = <&pinctrl_uart0>;
196 clocks = <&peri_clk 0>;
197 resets = <&peri_rst 0>;
203 reg = <0x54006900 0x40>;
206 pinctrl-0 = <&pinctrl_uart1>;
214 reg = <0x54006a00 0x40>;
217 pinctrl-0 = <&pinctrl_uart2>;
225 reg = <0x54006b00 0x40>;
228 pinctrl-0 = <&pinctrl_uart3>;
235 reg = <0x55000000 0x200>;
241 gpio-ranges = <&pinctrl 0 0 0>;
244 socionext,interrupt-ranges = <0 48 16>, <16 154 5>;
250 reg = <0x58780000 0x80>;
252 #size-cells = <0>;
255 pinctrl-0 = <&pinctrl_i2c0>;
264 reg = <0x58781000 0x80>;
266 #size-cells = <0>;
269 pinctrl-0 = <&pinctrl_i2c1>;
278 reg = <0x58782000 0x80>;
280 #size-cells = <0>;
283 pinctrl-0 = <&pinctrl_i2c2>;
292 reg = <0x58783000 0x80>;
294 #size-cells = <0>;
297 pinctrl-0 = <&pinctrl_i2c3>;
308 reg = <0x58785000 0x80>;
310 #size-cells = <0>;
320 reg = <0x58786000 0x80>;
322 #size-cells = <0>;
332 reg = <0x58c00000 0x400>;
336 pinctrl-0 = <&pinctrl_system_bus>;
341 reg = <0x59801000 0x400>;
347 reg = <0x59810000 0x400>;
363 reg = <0x59820000 0x200>;
379 reg = <0x5f800000 0x2000>;
389 reg = <0x5f900000 0x2000>;
392 ranges = <0 0x5f900000 0x2000>;
396 reg = <0x100 0x28>;
401 reg = <0x130 0x8>;
406 reg = <0x200 0x28>;
411 reg = <0x300 0x14>;
416 reg = <0x400 0x8>;
422 reg = <0x5fc10000 0x5300>;
430 reg = <0x5fc20000 0x200>;
437 reg = <0x60000200 0x20>;
445 reg = <0x60000600 0x20>;
453 reg = <0x60001000 0x1000>,
454 <0x60000100 0x100>;
462 reg = <0x61840000 0x10000>;
478 reg = <0x65a00000 0xcd00>;
482 pinctrl-0 = <&pinctrl_usb0>;
493 reg = <0x65b00000 0x400>;
496 ranges = <0 0x65b00000 0x400>;
498 usb0_rst: reset-controller@0 {
500 reg = <0x0 0x4>;
510 reg = <0x100 0x10>;
519 reg = <0x280 0x10>;
520 #phy-cells = <0>;
530 reg = <0x380 0x10>;
531 #phy-cells = <0>;
543 reg = <0x65c00000 0xcd00>;
547 pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb2>;
558 reg = <0x65d00000 0x400>;
561 ranges = <0 0x65d00000 0x400>;
563 usb1_rst: reset-controller@0 {
565 reg = <0x0 0x4>;
575 reg = <0x100 0x10>;
584 reg = <0x110 0x10>;
593 reg = <0x280 0x10>;
594 #phy-cells = <0>;
604 reg = <0x290 0x10>;
605 #phy-cells = <0>;
615 reg = <0x380 0x10>;
616 #phy-cells = <0>;
629 reg = <0x66000000 0x1000>, <0x66001000 0x1000>,
630 <0x66010000 0x10000>, <0x67000000 0x400000>;
632 pinctrl-0 = <&pinctrl_pcie>;
646 reg = <0x66038000 0x4000>;
647 #phy-cells = <0>;
658 reg = <0x68000000 0x20>, <0x68100000 0x1000>;
660 #size-cells = <0>;
663 pinctrl-0 = <&pinctrl_nand>;
673 reg = <0x68400000 0x800>;
676 pinctrl-0 = <&pinctrl_emmc>;
689 reg = <0x68800000 0x800>;
692 pinctrl-0 = <&pinctrl_sd>;
694 clocks = <&sd_clk 0>;
696 resets = <&sd_rst 0>;
702 socionext,syscon-uhs-mode = <&sdctrl 0>;