Lines Matching +full:uniphier +full:- +full:fi2c
1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 // Device Tree Source for UniPhier Pro4 SoC
5 // Copyright (C) 2015-2016 Socionext Inc.
8 #include <dt-bindings/gpio/uniphier-gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 compatible = "socionext,uniphier-pro4";
13 #address-cells = <1>;
14 #size-cells = <1>;
17 #address-cells = <1>;
18 #size-cells = <0>;
22 compatible = "arm,cortex-a9";
24 enable-method = "psci";
25 next-level-cache = <&l2>;
30 compatible = "arm,cortex-a9";
32 enable-method = "psci";
33 next-level-cache = <&l2>;
38 compatible = "arm,psci-0.2";
44 compatible = "fixed-clock";
45 #clock-cells = <0>;
46 clock-frequency = <25000000>;
49 arm_timer_clk: arm-timer {
50 #clock-cells = <0>;
51 compatible = "fixed-clock";
52 clock-frequency = <50000000>;
57 compatible = "simple-bus";
58 #address-cells = <1>;
59 #size-cells = <1>;
61 interrupt-parent = <&intc>;
63 l2: cache-controller@500c0000 {
64 compatible = "socionext,uniphier-system-cache";
69 cache-unified;
70 cache-size = <(768 * 1024)>;
71 cache-sets = <256>;
72 cache-line-size = <128>;
73 cache-level = <2>;
77 compatible = "socionext,uniphier-scssi";
80 #address-cells = <1>;
81 #size-cells = <0>;
83 pinctrl-names = "default";
84 pinctrl-0 = <&pinctrl_spi0>;
90 compatible = "socionext,uniphier-uart";
94 pinctrl-names = "default";
95 pinctrl-0 = <&pinctrl_uart0>;
101 compatible = "socionext,uniphier-uart";
105 pinctrl-names = "default";
106 pinctrl-0 = <&pinctrl_uart1>;
112 compatible = "socionext,uniphier-uart";
116 pinctrl-names = "default";
117 pinctrl-0 = <&pinctrl_uart2>;
123 compatible = "socionext,uniphier-uart";
127 pinctrl-names = "default";
128 pinctrl-0 = <&pinctrl_uart3>;
134 compatible = "socionext,uniphier-gpio";
136 interrupt-parent = <&aidet>;
137 interrupt-controller;
138 #interrupt-cells = <2>;
139 gpio-controller;
140 #gpio-cells = <2>;
141 gpio-ranges = <&pinctrl 0 0 0>;
142 gpio-ranges-group-names = "gpio_range";
144 socionext,interrupt-ranges = <0 48 16>, <16 154 5>;
148 compatible = "socionext,uniphier-fi2c";
151 #address-cells = <1>;
152 #size-cells = <0>;
154 pinctrl-names = "default";
155 pinctrl-0 = <&pinctrl_i2c0>;
158 clock-frequency = <100000>;
162 compatible = "socionext,uniphier-fi2c";
165 #address-cells = <1>;
166 #size-cells = <0>;
168 pinctrl-names = "default";
169 pinctrl-0 = <&pinctrl_i2c1>;
172 clock-frequency = <100000>;
176 compatible = "socionext,uniphier-fi2c";
179 #address-cells = <1>;
180 #size-cells = <0>;
182 pinctrl-names = "default";
183 pinctrl-0 = <&pinctrl_i2c2>;
186 clock-frequency = <100000>;
190 compatible = "socionext,uniphier-fi2c";
193 #address-cells = <1>;
194 #size-cells = <0>;
196 pinctrl-names = "default";
197 pinctrl-0 = <&pinctrl_i2c3>;
200 clock-frequency = <100000>;
205 /* chip-internal connection for DMD */
207 compatible = "socionext,uniphier-fi2c";
209 #address-cells = <1>;
210 #size-cells = <0>;
214 clock-frequency = <400000>;
217 /* chip-internal connection for HDMI */
219 compatible = "socionext,uniphier-fi2c";
221 #address-cells = <1>;
222 #size-cells = <0>;
226 clock-frequency = <400000>;
229 system_bus: system-bus@58c00000 {
230 compatible = "socionext,uniphier-system-bus";
233 #address-cells = <2>;
234 #size-cells = <1>;
235 pinctrl-names = "default";
236 pinctrl-0 = <&pinctrl_system_bus>;
240 compatible = "socionext,uniphier-smpctrl";
245 compatible = "socionext,uniphier-pro4-mioctrl",
246 "simple-mfd", "syscon";
249 mio_clk: clock-controller {
250 compatible = "socionext,uniphier-pro4-mio-clock";
251 #clock-cells = <1>;
254 mio_rst: reset-controller {
255 compatible = "socionext,uniphier-pro4-mio-reset";
256 #reset-cells = <1>;
261 compatible = "socionext,uniphier-pro4-perictrl",
262 "simple-mfd", "syscon";
265 peri_clk: clock-controller {
266 compatible = "socionext,uniphier-pro4-peri-clock";
267 #clock-cells = <1>;
270 peri_rst: reset-controller {
271 compatible = "socionext,uniphier-pro4-peri-reset";
272 #reset-cells = <1>;
276 dmac: dma-controller@5a000000 {
277 compatible = "socionext,uniphier-mio-dmac";
289 #dma-cells = <1>;
293 compatible = "socionext,uniphier-sd-v2.91";
297 pinctrl-names = "default", "uhs";
298 pinctrl-0 = <&pinctrl_sd>;
299 pinctrl-1 = <&pinctrl_sd_uhs>;
301 reset-names = "host", "bridge";
303 dma-names = "rx-tx";
305 bus-width = <4>;
306 cap-sd-highspeed;
307 sd-uhs-sdr12;
308 sd-uhs-sdr25;
309 sd-uhs-sdr50;
310 socionext,syscon-uhs-mode = <&mioctrl 0>;
314 compatible = "socionext,uniphier-sd-v2.91";
318 pinctrl-names = "default";
319 pinctrl-0 = <&pinctrl_emmc>;
321 reset-names = "host", "bridge", "hw";
323 dma-names = "rx-tx";
325 bus-width = <8>;
326 cap-mmc-highspeed;
327 cap-mmc-hw-reset;
328 non-removable;
332 compatible = "socionext,uniphier-sd-v2.91";
336 pinctrl-names = "default";
337 pinctrl-0 = <&pinctrl_sd1>;
339 reset-names = "host", "bridge";
341 dma-names = "rx-tx";
343 bus-width = <4>;
344 cap-sd-highspeed;
348 compatible = "socionext,uniphier-ehci", "generic-ehci";
352 pinctrl-names = "default";
353 pinctrl-0 = <&pinctrl_usb2>;
358 phy-names = "usb";
360 has-transaction-translator;
364 compatible = "socionext,uniphier-ehci", "generic-ehci";
368 pinctrl-names = "default";
369 pinctrl-0 = <&pinctrl_usb3>;
374 phy-names = "usb";
376 has-transaction-translator;
380 compatible = "socionext,uniphier-pro4-soc-glue",
381 "simple-mfd", "syscon";
385 compatible = "socionext,uniphier-pro4-pinctrl";
388 usb-hub {
389 compatible = "socionext,uniphier-pro4-usb2-phy";
390 #address-cells = <1>;
391 #size-cells = <0>;
395 #phy-cells = <0>;
400 #phy-cells = <0>;
405 #phy-cells = <0>;
406 vbus-supply = <&usb0_vbus>;
411 #phy-cells = <0>;
412 vbus-supply = <&usb1_vbus>;
416 sg_clk: clock-controller {
417 compatible = "socionext,uniphier-pro4-sg-clock";
418 #clock-cells = <1>;
423 compatible = "socionext,uniphier-pro4-soc-glue-debug",
424 "simple-mfd", "syscon";
426 #address-cells = <1>;
427 #size-cells = <1>;
431 compatible = "socionext,uniphier-efuse";
436 compatible = "socionext,uniphier-efuse";
441 compatible = "socionext,uniphier-efuse";
446 xdmac: dma-controller@5fc10000 {
447 compatible = "socionext,uniphier-xdmac";
450 dma-channels = <16>;
451 #dma-cells = <2>;
454 aidet: interrupt-controller@5fc20000 {
455 compatible = "socionext,uniphier-pro4-aidet";
457 interrupt-controller;
458 #interrupt-cells = <2>;
462 compatible = "arm,cortex-a9-global-timer";
470 compatible = "arm,cortex-a9-twd-timer";
477 intc: interrupt-controller@60001000 {
478 compatible = "arm,cortex-a9-gic";
481 #interrupt-cells = <3>;
482 interrupt-controller;
486 compatible = "socionext,uniphier-pro4-sysctrl",
487 "simple-mfd", "syscon";
490 sys_clk: clock-controller {
491 compatible = "socionext,uniphier-pro4-clock";
492 #clock-cells = <1>;
495 sys_rst: reset-controller {
496 compatible = "socionext,uniphier-pro4-reset";
497 #reset-cells = <1>;
502 compatible = "socionext,uniphier-pro4-ave4";
506 pinctrl-names = "default";
507 pinctrl-0 = <&pinctrl_ether_rgmii>;
508 clock-names = "gio", "ether", "ether-gb", "ether-phy";
511 reset-names = "gio", "ether";
513 phy-mode = "rgmii";
514 local-mac-address = [00 00 00 00 00 00];
515 socionext,syscon-phy-mode = <&soc_glue 0>;
518 #address-cells = <1>;
519 #size-cells = <0>;
524 compatible = "socionext,uniphier-pro4-ahci",
525 "generic-ahci";
531 ports-implemented = <1>;
533 assigned-clocks = <&sg_clk 0>;
534 assigned-clock-rates = <25000000>;
537 sata-controller@65700000 {
538 compatible = "socionext,uniphier-pxs2-ahci-glue",
539 "simple-mfd";
541 #address-cells = <1>;
542 #size-cells = <1>;
545 ahci0_rst: reset-controller@0 {
546 compatible = "socionext,uniphier-pro4-ahci-reset";
548 clock-names = "gio", "link";
550 reset-names = "gio", "link";
552 #reset-cells = <1>;
556 compatible = "socionext,uniphier-pro4-ahci-phy";
558 clock-names = "link", "gio";
560 reset-names = "link", "gio", "phy",
566 #phy-cells = <0>;
571 compatible = "socionext,uniphier-pro4-ahci",
572 "generic-ahci";
578 ports-implemented = <1>;
580 assigned-clocks = <&sg_clk 0>;
581 assigned-clock-rates = <25000000>;
584 sata-controller@65900000 {
585 compatible = "socionext,uniphier-pro4-ahci-glue",
586 "simple-mfd";
588 #address-cells = <1>;
589 #size-cells = <1>;
592 ahci1_rst: reset-controller@0 {
593 compatible = "socionext,uniphier-pro4-ahci-reset";
595 clock-names = "gio", "link";
597 reset-names = "gio", "link";
599 #reset-cells = <1>;
603 compatible = "socionext,uniphier-pro4-ahci-phy";
605 clock-names = "link", "gio";
607 reset-names = "link", "gio", "phy",
613 #phy-cells = <0>;
618 compatible = "socionext,uniphier-dwc3", "snps,dwc3";
621 interrupt-names = "host", "peripheral";
624 pinctrl-names = "default";
625 pinctrl-0 = <&pinctrl_usb0>;
626 clock-names = "ref", "bus_early", "suspend";
633 usb-controller@65b00000 {
634 compatible = "socionext,uniphier-pro4-dwc3-glue",
635 "simple-mfd";
637 #address-cells = <1>;
638 #size-cells = <1>;
642 compatible = "socionext,uniphier-pro4-usb3-regulator";
644 clock-names = "gio", "link";
646 reset-names = "gio", "link";
651 compatible = "socionext,uniphier-pro4-usb3-ssphy";
653 #phy-cells = <0>;
654 clock-names = "gio", "link";
656 reset-names = "gio", "link";
658 vbus-supply = <&usb0_vbus>;
661 usb0_rst: reset-controller@40 {
662 compatible = "socionext,uniphier-pro4-usb3-reset";
664 #reset-cells = <1>;
665 clock-names = "gio", "link";
667 reset-names = "gio", "link";
673 compatible = "socionext,uniphier-dwc3", "snps,dwc3";
676 interrupt-names = "host", "peripheral";
679 pinctrl-names = "default";
680 pinctrl-0 = <&pinctrl_usb1>;
681 clock-names = "ref", "bus_early", "suspend";
688 usb-controller@65d00000 {
689 compatible = "socionext,uniphier-pro4-dwc3-glue",
690 "simple-mfd";
692 #address-cells = <1>;
693 #size-cells = <1>;
697 compatible = "socionext,uniphier-pro4-usb3-regulator";
699 clock-names = "gio", "link";
701 reset-names = "gio", "link";
705 usb1_rst: reset-controller@40 {
706 compatible = "socionext,uniphier-pro4-usb3-reset";
708 #reset-cells = <1>;
709 clock-names = "gio", "link";
711 reset-names = "gio", "link";
716 nand: nand-controller@68000000 {
717 compatible = "socionext,uniphier-denali-nand-v5a";
719 reg-names = "nand_data", "denali_reg";
721 #address-cells = <1>;
722 #size-cells = <0>;
724 pinctrl-names = "default";
725 pinctrl-0 = <&pinctrl_nand>;
726 clock-names = "nand", "nand_x", "ecc";
728 reset-names = "nand", "reg";
734 #include "uniphier-pinctrl.dtsi"