Lines Matching +full:uniphier +full:- +full:uart
1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 // Device Tree Source for UniPhier LD4 SoC
5 // Copyright (C) 2015-2016 Socionext Inc.
8 #include <dt-bindings/gpio/uniphier-gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 compatible = "socionext,uniphier-ld4";
13 #address-cells = <1>;
14 #size-cells = <1>;
17 #address-cells = <1>;
18 #size-cells = <0>;
22 compatible = "arm,cortex-a9";
24 enable-method = "psci";
25 next-level-cache = <&l2>;
30 compatible = "arm,psci-0.2";
36 compatible = "fixed-clock";
37 #clock-cells = <0>;
38 clock-frequency = <24576000>;
41 arm_timer_clk: arm-timer {
42 #clock-cells = <0>;
43 compatible = "fixed-clock";
44 clock-frequency = <50000000>;
49 compatible = "simple-bus";
50 #address-cells = <1>;
51 #size-cells = <1>;
53 interrupt-parent = <&intc>;
55 l2: cache-controller@500c0000 {
56 compatible = "socionext,uniphier-system-cache";
61 cache-unified;
62 cache-size = <(512 * 1024)>;
63 cache-sets = <256>;
64 cache-line-size = <128>;
65 cache-level = <2>;
69 compatible = "socionext,uniphier-scssi";
72 #address-cells = <1>;
73 #size-cells = <0>;
75 pinctrl-names = "default";
76 pinctrl-0 = <&pinctrl_spi0>;
82 compatible = "socionext,uniphier-uart";
86 pinctrl-names = "default";
87 pinctrl-0 = <&pinctrl_uart0>;
93 compatible = "socionext,uniphier-uart";
97 pinctrl-names = "default";
98 pinctrl-0 = <&pinctrl_uart1>;
104 compatible = "socionext,uniphier-uart";
108 pinctrl-names = "default";
109 pinctrl-0 = <&pinctrl_uart2>;
115 compatible = "socionext,uniphier-uart";
119 pinctrl-names = "default";
120 pinctrl-0 = <&pinctrl_uart3>;
126 compatible = "socionext,uniphier-gpio";
128 interrupt-parent = <&aidet>;
129 interrupt-controller;
130 #interrupt-cells = <2>;
131 gpio-controller;
132 #gpio-cells = <2>;
133 gpio-ranges = <&pinctrl 0 0 0>;
134 gpio-ranges-group-names = "gpio_range";
136 socionext,interrupt-ranges = <0 48 13>, <14 62 2>;
140 compatible = "socionext,uniphier-i2c";
143 #address-cells = <1>;
144 #size-cells = <0>;
146 pinctrl-names = "default";
147 pinctrl-0 = <&pinctrl_i2c0>;
150 clock-frequency = <100000>;
154 compatible = "socionext,uniphier-i2c";
157 #address-cells = <1>;
158 #size-cells = <0>;
160 pinctrl-names = "default";
161 pinctrl-0 = <&pinctrl_i2c1>;
164 clock-frequency = <100000>;
167 /* chip-internal connection for DMD */
169 compatible = "socionext,uniphier-i2c";
171 #address-cells = <1>;
172 #size-cells = <0>;
174 pinctrl-names = "default";
175 pinctrl-0 = <&pinctrl_i2c2>;
178 clock-frequency = <400000>;
182 compatible = "socionext,uniphier-i2c";
185 #address-cells = <1>;
186 #size-cells = <0>;
188 pinctrl-names = "default";
189 pinctrl-0 = <&pinctrl_i2c3>;
192 clock-frequency = <100000>;
195 system_bus: system-bus@58c00000 {
196 compatible = "socionext,uniphier-system-bus";
199 #address-cells = <2>;
200 #size-cells = <1>;
201 pinctrl-names = "default";
202 pinctrl-0 = <&pinctrl_system_bus>;
206 compatible = "socionext,uniphier-smpctrl";
211 compatible = "socionext,uniphier-ld4-mioctrl",
212 "simple-mfd", "syscon";
215 mio_clk: clock-controller {
216 compatible = "socionext,uniphier-ld4-mio-clock";
217 #clock-cells = <1>;
220 mio_rst: reset-controller {
221 compatible = "socionext,uniphier-ld4-mio-reset";
222 #reset-cells = <1>;
227 compatible = "socionext,uniphier-ld4-perictrl",
228 "simple-mfd", "syscon";
231 peri_clk: clock-controller {
232 compatible = "socionext,uniphier-ld4-peri-clock";
233 #clock-cells = <1>;
236 peri_rst: reset-controller {
237 compatible = "socionext,uniphier-ld4-peri-reset";
238 #reset-cells = <1>;
242 dmac: dma-controller@5a000000 {
243 compatible = "socionext,uniphier-mio-dmac";
254 #dma-cells = <1>;
258 compatible = "socionext,uniphier-sd-v2.91";
262 pinctrl-names = "default", "uhs";
263 pinctrl-0 = <&pinctrl_sd>;
264 pinctrl-1 = <&pinctrl_sd_uhs>;
266 reset-names = "host", "bridge";
268 dma-names = "rx-tx";
270 bus-width = <4>;
271 cap-sd-highspeed;
272 sd-uhs-sdr12;
273 sd-uhs-sdr25;
274 sd-uhs-sdr50;
278 compatible = "socionext,uniphier-sd-v2.91";
282 pinctrl-names = "default";
283 pinctrl-0 = <&pinctrl_emmc>;
285 reset-names = "host", "bridge", "hw";
287 dma-names = "rx-tx";
289 bus-width = <8>;
290 cap-mmc-highspeed;
291 cap-mmc-hw-reset;
292 non-removable;
296 compatible = "socionext,uniphier-ehci", "generic-ehci";
300 pinctrl-names = "default";
301 pinctrl-0 = <&pinctrl_usb0>;
306 has-transaction-translator;
310 compatible = "socionext,uniphier-ehci", "generic-ehci";
314 pinctrl-names = "default";
315 pinctrl-0 = <&pinctrl_usb1>;
320 has-transaction-translator;
324 compatible = "socionext,uniphier-ehci", "generic-ehci";
328 pinctrl-names = "default";
329 pinctrl-0 = <&pinctrl_usb2>;
334 has-transaction-translator;
338 compatible = "socionext,uniphier-ld4-soc-glue",
339 "simple-mfd", "syscon";
343 compatible = "socionext,uniphier-ld4-pinctrl";
348 compatible = "socionext,uniphier-ld4-soc-glue-debug",
349 "simple-mfd", "syscon";
351 #address-cells = <1>;
352 #size-cells = <1>;
356 compatible = "socionext,uniphier-efuse";
361 compatible = "socionext,uniphier-efuse";
367 compatible = "arm,cortex-a9-global-timer";
375 compatible = "arm,cortex-a9-twd-timer";
382 intc: interrupt-controller@60001000 {
383 compatible = "arm,cortex-a9-gic";
386 #interrupt-cells = <3>;
387 interrupt-controller;
390 aidet: interrupt-controller@61830000 {
391 compatible = "socionext,uniphier-ld4-aidet";
393 interrupt-controller;
394 #interrupt-cells = <2>;
398 compatible = "socionext,uniphier-ld4-sysctrl",
399 "simple-mfd", "syscon";
402 sys_clk: clock-controller {
403 compatible = "socionext,uniphier-ld4-clock";
404 #clock-cells = <1>;
407 sys_rst: reset-controller {
408 compatible = "socionext,uniphier-ld4-reset";
409 #reset-cells = <1>;
413 nand: nand-controller@68000000 {
414 compatible = "socionext,uniphier-denali-nand-v5a";
416 reg-names = "nand_data", "denali_reg";
418 #address-cells = <1>;
419 #size-cells = <0>;
421 pinctrl-names = "default";
422 pinctrl-0 = <&pinctrl_nand>;
423 clock-names = "nand", "nand_x", "ecc";
425 reset-names = "nand", "reg";
431 #include "uniphier-pinctrl.dtsi"