Lines Matching +full:clock +full:- +full:master
1 // SPDX-License-Identifier: GPL-2.0
14 #include <dt-bindings/clock/exynos5420.h>
15 #include <dt-bindings/clock/exynos-audss-clk.h>
16 #include <dt-bindings/interrupt-controller/arm-gic.h>
37 bus_disp1: bus-disp1 {
38 compatible = "samsung,exynos-bus";
39 clocks = <&clock CLK_DOUT_ACLK400_DISP1>;
40 clock-names = "bus";
44 bus_disp1_fimd: bus-disp1-fimd {
45 compatible = "samsung,exynos-bus";
46 clocks = <&clock CLK_DOUT_ACLK300_DISP1>;
47 clock-names = "bus";
51 bus_fsys: bus-fsys {
52 compatible = "samsung,exynos-bus";
53 clocks = <&clock CLK_DOUT_ACLK200_FSYS>;
54 clock-names = "bus";
58 bus_fsys2: bus-fsys2 {
59 compatible = "samsung,exynos-bus";
60 clocks = <&clock CLK_DOUT_ACLK200_FSYS2>;
61 clock-names = "bus";
65 bus_fsys_apb: bus-fsys-apb {
66 compatible = "samsung,exynos-bus";
67 clocks = <&clock CLK_DOUT_PCLK200_FSYS>;
68 clock-names = "bus";
72 bus_g2d: bus-g2d {
73 compatible = "samsung,exynos-bus";
74 clocks = <&clock CLK_DOUT_ACLK333_G2D>;
75 clock-names = "bus";
79 bus_g2d_acp: bus-g2d-acp {
80 compatible = "samsung,exynos-bus";
81 clocks = <&clock CLK_DOUT_ACLK266_G2D>;
82 clock-names = "bus";
85 bus_gen: bus-gen {
86 compatible = "samsung,exynos-bus";
87 clocks = <&clock CLK_DOUT_ACLK266>;
88 clock-names = "bus";
92 bus_gscl_scaler: bus-gscl-scaler {
93 compatible = "samsung,exynos-bus";
94 clocks = <&clock CLK_DOUT_ACLK300_GSCL>;
95 clock-names = "bus";
99 bus_jpeg: bus-jpeg {
100 compatible = "samsung,exynos-bus";
101 clocks = <&clock CLK_DOUT_ACLK300_JPEG>;
102 clock-names = "bus";
106 bus_jpeg_apb: bus-jpeg-apb {
107 compatible = "samsung,exynos-bus";
108 clocks = <&clock CLK_DOUT_ACLK166>;
109 clock-names = "bus";
113 bus_mfc: bus-mfc {
114 compatible = "samsung,exynos-bus";
115 clocks = <&clock CLK_DOUT_ACLK333>;
116 clock-names = "bus";
120 bus_mscl: bus-mscl {
121 compatible = "samsung,exynos-bus";
122 clocks = <&clock CLK_DOUT_ACLK400_MSCL>;
123 clock-names = "bus";
127 bus_noc: bus-noc {
128 compatible = "samsung,exynos-bus";
129 clocks = <&clock CLK_DOUT_ACLK100_NOC>;
130 clock-names = "bus";
134 bus_peri: bus-peri {
135 compatible = "samsung,exynos-bus";
136 clocks = <&clock CLK_DOUT_ACLK66>;
137 clock-names = "bus";
141 bus_wcore: bus-wcore {
142 compatible = "samsung,exynos-bus";
143 clocks = <&clock CLK_DOUT_ACLK400_WCORE>;
144 clock-names = "bus";
150 * by exynos5420-cpus.dtsi or exynos5422-cpus.dtsi.
153 cluster_a15_opp_table: opp-table-0 {
154 compatible = "operating-points-v2";
155 opp-shared;
157 opp-1800000000 {
158 opp-hz = /bits/ 64 <1800000000>;
159 opp-microvolt = <1250000 1250000 1500000>;
160 clock-latency-ns = <140000>;
162 opp-1700000000 {
163 opp-hz = /bits/ 64 <1700000000>;
164 opp-microvolt = <1212500 1212500 1500000>;
165 clock-latency-ns = <140000>;
167 opp-1600000000 {
168 opp-hz = /bits/ 64 <1600000000>;
169 opp-microvolt = <1175000 1175000 1500000>;
170 clock-latency-ns = <140000>;
172 opp-1500000000 {
173 opp-hz = /bits/ 64 <1500000000>;
174 opp-microvolt = <1137500 1137500 1500000>;
175 clock-latency-ns = <140000>;
177 opp-1400000000 {
178 opp-hz = /bits/ 64 <1400000000>;
179 opp-microvolt = <1112500 1112500 1500000>;
180 clock-latency-ns = <140000>;
182 opp-1300000000 {
183 opp-hz = /bits/ 64 <1300000000>;
184 opp-microvolt = <1062500 1062500 1500000>;
185 clock-latency-ns = <140000>;
187 opp-1200000000 {
188 opp-hz = /bits/ 64 <1200000000>;
189 opp-microvolt = <1037500 1037500 1500000>;
190 clock-latency-ns = <140000>;
192 opp-1100000000 {
193 opp-hz = /bits/ 64 <1100000000>;
194 opp-microvolt = <1012500 1012500 1500000>;
195 clock-latency-ns = <140000>;
197 opp-1000000000 {
198 opp-hz = /bits/ 64 <1000000000>;
199 opp-microvolt = < 987500 987500 1500000>;
200 clock-latency-ns = <140000>;
202 opp-900000000 {
203 opp-hz = /bits/ 64 <900000000>;
204 opp-microvolt = < 962500 962500 1500000>;
205 clock-latency-ns = <140000>;
207 opp-800000000 {
208 opp-hz = /bits/ 64 <800000000>;
209 opp-microvolt = < 937500 937500 1500000>;
210 clock-latency-ns = <140000>;
212 opp-700000000 {
213 opp-hz = /bits/ 64 <700000000>;
214 opp-microvolt = < 912500 912500 1500000>;
215 clock-latency-ns = <140000>;
219 cluster_a7_opp_table: opp-table-1 {
220 compatible = "operating-points-v2";
221 opp-shared;
223 opp-1300000000 {
224 opp-hz = /bits/ 64 <1300000000>;
225 opp-microvolt = <1275000>;
226 clock-latency-ns = <140000>;
228 opp-1200000000 {
229 opp-hz = /bits/ 64 <1200000000>;
230 opp-microvolt = <1212500>;
231 clock-latency-ns = <140000>;
233 opp-1100000000 {
234 opp-hz = /bits/ 64 <1100000000>;
235 opp-microvolt = <1162500>;
236 clock-latency-ns = <140000>;
238 opp-1000000000 {
239 opp-hz = /bits/ 64 <1000000000>;
240 opp-microvolt = <1112500>;
241 clock-latency-ns = <140000>;
243 opp-900000000 {
244 opp-hz = /bits/ 64 <900000000>;
245 opp-microvolt = <1062500>;
246 clock-latency-ns = <140000>;
248 opp-800000000 {
249 opp-hz = /bits/ 64 <800000000>;
250 opp-microvolt = <1025000>;
251 clock-latency-ns = <140000>;
253 opp-700000000 {
254 opp-hz = /bits/ 64 <700000000>;
255 opp-microvolt = <975000>;
256 clock-latency-ns = <140000>;
258 opp-600000000 {
259 opp-hz = /bits/ 64 <600000000>;
260 opp-microvolt = <937500>;
261 clock-latency-ns = <140000>;
267 compatible = "arm,cci-400";
268 #address-cells = <1>;
269 #size-cells = <1>;
273 cci_control0: slave-if@4000 {
274 compatible = "arm,cci-400-ctrl-if";
275 interface-type = "ace";
278 cci_control1: slave-if@5000 {
279 compatible = "arm,cci-400-ctrl-if";
280 interface-type = "ace";
285 clock: clock-controller@10010000 { label
286 compatible = "samsung,exynos5420-clock", "syscon";
288 #clock-cells = <1>;
291 clock_audss: audss-clock-controller@3810000 {
292 compatible = "samsung,exynos5420-audss-clock";
294 #clock-cells = <1>;
295 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MAU_EPLL>,
296 <&clock CLK_SCLK_MAUDIO0>, <&clock CLK_SCLK_MAUPCM0>;
297 clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
298 power-domains = <&mau_pd>;
302 compatible = "samsung,mfc-v7";
305 clocks = <&clock CLK_MFC>;
306 clock-names = "mfc";
307 power-domains = <&mfc_pd>;
309 iommu-names = "left", "right";
313 compatible = "samsung,exynos5420-dw-mshc-smu";
315 #address-cells = <1>;
316 #size-cells = <0>;
318 clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>;
319 clock-names = "biu", "ciu";
320 fifo-depth = <0x40>;
325 compatible = "samsung,exynos5420-dw-mshc-smu";
327 #address-cells = <1>;
328 #size-cells = <0>;
330 clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>;
331 clock-names = "biu", "ciu";
332 fifo-depth = <0x40>;
337 compatible = "samsung,exynos5420-dw-mshc";
339 #address-cells = <1>;
340 #size-cells = <0>;
342 clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>;
343 clock-names = "biu", "ciu";
344 fifo-depth = <0x40>;
348 dmc: memory-controller@10c20000 {
349 compatible = "samsung,exynos5422-dmc";
351 clocks = <&clock CLK_FOUT_SPLL>,
352 <&clock CLK_MOUT_SCLK_SPLL>,
353 <&clock CLK_FF_DOUT_SPLL2>,
354 <&clock CLK_FOUT_BPLL>,
355 <&clock CLK_MOUT_BPLL>,
356 <&clock CLK_SCLK_BPLL>,
357 <&clock CLK_MOUT_MX_MSPLL_CCORE>,
358 <&clock CLK_MOUT_MCLK_CDREX>;
359 clock-names = "fout_spll",
367 samsung,syscon-clk = <&clock>;
372 compatible = "samsung,exynos5420-nocp";
378 compatible = "samsung,exynos5420-nocp";
384 compatible = "samsung,exynos5420-nocp";
390 compatible = "samsung,exynos5420-nocp";
396 compatible = "samsung,exynos5420-nocp";
402 compatible = "samsung,exynos5420-nocp";
408 compatible = "samsung,exynos-ppmu";
410 clocks = <&clock CLK_PCLK_PPMU_DREX0_0>;
411 clock-names = "ppmu";
413 ppmu_event3_dmc0_0: ppmu-event3-dmc0-0 {
414 event-name = "ppmu-event3-dmc0-0";
420 compatible = "samsung,exynos-ppmu";
422 clocks = <&clock CLK_PCLK_PPMU_DREX0_1>;
423 clock-names = "ppmu";
425 ppmu_event3_dmc0_1: ppmu-event3-dmc0-1 {
426 event-name = "ppmu-event3-dmc0-1";
432 compatible = "samsung,exynos-ppmu";
434 clocks = <&clock CLK_PCLK_PPMU_DREX1_0>;
435 clock-names = "ppmu";
437 ppmu_event3_dmc1_0: ppmu-event3-dmc1-0 {
438 event-name = "ppmu-event3-dmc1-0";
444 compatible = "samsung,exynos-ppmu";
446 clocks = <&clock CLK_PCLK_PPMU_DREX1_1>;
447 clock-names = "ppmu";
449 ppmu_event3_dmc1_1: ppmu-event3-dmc1-1 {
450 event-name = "ppmu-event3-dmc1-1";
455 gsc_pd: power-domain@10044000 {
456 compatible = "samsung,exynos4210-pd";
458 #power-domain-cells = <0>;
462 isp_pd: power-domain@10044020 {
463 compatible = "samsung,exynos4210-pd";
465 #power-domain-cells = <0>;
469 mfc_pd: power-domain@10044060 {
470 compatible = "samsung,exynos4210-pd";
472 #power-domain-cells = <0>;
476 g3d_pd: power-domain@10044080 {
477 compatible = "samsung,exynos4210-pd";
479 #power-domain-cells = <0>;
483 disp_pd: power-domain@100440c0 {
484 compatible = "samsung,exynos4210-pd";
486 #power-domain-cells = <0>;
490 mau_pd: power-domain@100440e0 {
491 compatible = "samsung,exynos4210-pd";
493 #power-domain-cells = <0>;
497 msc_pd: power-domain@10044120 {
498 compatible = "samsung,exynos4210-pd";
500 #power-domain-cells = <0>;
505 compatible = "samsung,exynos5420-pinctrl";
509 wakeup-interrupt-controller {
510 compatible = "samsung,exynos4210-wakeup-eint";
511 interrupt-parent = <&gic>;
517 compatible = "samsung,exynos5420-pinctrl";
523 compatible = "samsung,exynos5420-pinctrl";
529 compatible = "samsung,exynos5420-pinctrl";
535 compatible = "samsung,exynos5420-pinctrl";
538 power-domains = <&mau_pd>;
541 adma: dma-controller@3880000 {
546 clock-names = "apb_pclk";
547 #dma-cells = <1>;
548 power-domains = <&mau_pd>;
551 pdma0: dma-controller@121a0000 {
555 clocks = <&clock CLK_PDMA0>;
556 clock-names = "apb_pclk";
557 #dma-cells = <1>;
560 pdma1: dma-controller@121b0000 {
564 clocks = <&clock CLK_PDMA1>;
565 clock-names = "apb_pclk";
566 #dma-cells = <1>;
569 mdma0: dma-controller@10800000 {
573 clocks = <&clock CLK_MDMA0>;
574 clock-names = "apb_pclk";
575 #dma-cells = <1>;
578 mdma1: dma-controller@11c10000 {
582 clocks = <&clock CLK_MDMA1>;
583 clock-names = "apb_pclk";
584 #dma-cells = <1>;
586 * MDMA1 can support both secure and non-secure
596 compatible = "samsung,exynos5420-i2s";
601 dma-names = "tx", "rx", "tx-sec";
605 clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
606 #clock-cells = <1>;
607 clock-output-names = "i2s_cdclk0";
608 #sound-dai-cells = <1>;
609 samsung,idma-addr = <0x03000000>;
610 pinctrl-names = "default";
611 pinctrl-0 = <&i2s0_bus>;
612 power-domains = <&mau_pd>;
617 compatible = "samsung,exynos5420-i2s";
621 dma-names = "tx", "rx";
622 clocks = <&clock CLK_I2S1>, <&clock CLK_SCLK_I2S1>;
623 clock-names = "iis", "i2s_opclk0";
624 #clock-cells = <1>;
625 clock-output-names = "i2s_cdclk1";
626 #sound-dai-cells = <1>;
627 pinctrl-names = "default";
628 pinctrl-0 = <&i2s1_bus>;
633 compatible = "samsung,exynos5420-i2s";
637 dma-names = "tx", "rx";
638 clocks = <&clock CLK_I2S2>, <&clock CLK_SCLK_I2S2>;
639 clock-names = "iis", "i2s_opclk0";
640 #clock-cells = <1>;
641 clock-output-names = "i2s_cdclk2";
642 #sound-dai-cells = <1>;
643 pinctrl-names = "default";
644 pinctrl-0 = <&i2s2_bus>;
649 compatible = "samsung,exynos4210-spi";
654 dma-names = "tx", "rx";
655 #address-cells = <1>;
656 #size-cells = <0>;
657 pinctrl-names = "default";
658 pinctrl-0 = <&spi0_bus>;
659 clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
660 clock-names = "spi", "spi_busclk0";
665 compatible = "samsung,exynos4210-spi";
670 dma-names = "tx", "rx";
671 #address-cells = <1>;
672 #size-cells = <0>;
673 pinctrl-names = "default";
674 pinctrl-0 = <&spi1_bus>;
675 clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
676 clock-names = "spi", "spi_busclk0";
681 compatible = "samsung,exynos4210-spi";
686 dma-names = "tx", "rx";
687 #address-cells = <1>;
688 #size-cells = <0>;
689 pinctrl-names = "default";
690 pinctrl-0 = <&spi2_bus>;
691 clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
692 clock-names = "spi", "spi_busclk0";
697 compatible = "samsung,exynos5410-mipi-dsi";
701 phy-names = "dsim";
702 clocks = <&clock CLK_DSIM1>, <&clock CLK_SCLK_MIPI1>;
703 clock-names = "bus_clk", "pll_clk";
704 #address-cells = <1>;
705 #size-cells = <0>;
710 compatible = "samsung,exynos5250-hsi2c";
713 #address-cells = <1>;
714 #size-cells = <0>;
715 pinctrl-names = "default";
716 pinctrl-0 = <&i2c8_hs_bus>;
717 clocks = <&clock CLK_USI4>;
718 clock-names = "hsi2c";
723 compatible = "samsung,exynos5250-hsi2c";
726 #address-cells = <1>;
727 #size-cells = <0>;
728 pinctrl-names = "default";
729 pinctrl-0 = <&i2c9_hs_bus>;
730 clocks = <&clock CLK_USI5>;
731 clock-names = "hsi2c";
736 compatible = "samsung,exynos5250-hsi2c";
739 #address-cells = <1>;
740 #size-cells = <0>;
741 pinctrl-names = "default";
742 pinctrl-0 = <&i2c10_hs_bus>;
743 clocks = <&clock CLK_USI6>;
744 clock-names = "hsi2c";
749 compatible = "samsung,exynos5420-hdmi";
752 clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
753 <&clock CLK_DOUT_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
754 <&clock CLK_MOUT_HDMI>;
755 clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
758 samsung,syscon-phandle = <&pmu_system_controller>;
760 power-domains = <&disp_pd>;
761 #sound-dai-cells = <0>;
764 hdmiphy: hdmi-phy@145d0000 {
769 compatible = "samsung,s5p-cec";
772 clocks = <&clock CLK_HDMI_CEC>;
773 clock-names = "hdmicec";
774 samsung,syscon-phandle = <&pmu_system_controller>;
775 hdmi-phandle = <&hdmi>;
776 pinctrl-names = "default";
777 pinctrl-0 = <&hdmi_cec>;
782 compatible = "samsung,exynos5420-mixer";
785 clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
786 <&clock CLK_SCLK_HDMI>;
787 clock-names = "mixer", "hdmi", "sclk_hdmi";
788 power-domains = <&disp_pd>;
794 compatible = "samsung,exynos5250-rotator";
797 clocks = <&clock CLK_ROTATOR>;
798 clock-names = "rotator";
802 gsc_0: video-scaler@13e00000 {
803 compatible = "samsung,exynos5420-gsc", "samsung,exynos5-gsc";
806 clocks = <&clock CLK_GSCL0>;
807 clock-names = "gscl";
808 power-domains = <&gsc_pd>;
812 gsc_1: video-scaler@13e10000 {
813 compatible = "samsung,exynos5420-gsc", "samsung,exynos5-gsc";
816 clocks = <&clock CLK_GSCL1>;
817 clock-names = "gscl";
818 power-domains = <&gsc_pd>;
823 compatible = "samsung,exynos5420-mali", "arm,mali-t628";
828 interrupt-names = "job", "mmu", "gpu";
830 clocks = <&clock CLK_G3D>;
831 clock-names = "core";
832 power-domains = <&g3d_pd>;
833 operating-points-v2 = <&gpu_opp_table>;
836 #cooling-cells = <2>;
838 gpu_opp_table: opp-table {
839 compatible = "operating-points-v2";
841 opp-177000000 {
842 opp-hz = /bits/ 64 <177000000>;
843 opp-microvolt = <812500>;
845 opp-266000000 {
846 opp-hz = /bits/ 64 <266000000>;
847 opp-microvolt = <862500>;
849 opp-350000000 {
850 opp-hz = /bits/ 64 <350000000>;
851 opp-microvolt = <912500>;
853 opp-420000000 {
854 opp-hz = /bits/ 64 <420000000>;
855 opp-microvolt = <962500>;
857 opp-480000000 {
858 opp-hz = /bits/ 64 <480000000>;
859 opp-microvolt = <1000000>;
861 opp-543000000 {
862 opp-hz = /bits/ 64 <543000000>;
863 opp-microvolt = <1037500>;
865 opp-600000000 {
866 opp-hz = /bits/ 64 <600000000>;
867 opp-microvolt = <1150000>;
873 compatible = "samsung,exynos5420-scaler";
876 clocks = <&clock CLK_MSCL0>;
877 clock-names = "mscl";
878 power-domains = <&msc_pd>;
883 compatible = "samsung,exynos5420-scaler";
886 clocks = <&clock CLK_MSCL1>;
887 clock-names = "mscl";
888 power-domains = <&msc_pd>;
893 compatible = "samsung,exynos5420-scaler";
896 clocks = <&clock CLK_MSCL2>;
897 clock-names = "mscl";
898 power-domains = <&msc_pd>;
903 compatible = "samsung,exynos5420-jpeg";
906 clock-names = "jpeg";
907 clocks = <&clock CLK_JPEG>;
912 compatible = "samsung,exynos5420-jpeg";
915 clock-names = "jpeg";
916 clocks = <&clock CLK_JPEG2>;
920 pmu_system_controller: system-controller@10040000 {
921 compatible = "samsung,exynos5420-pmu", "simple-mfd", "syscon";
923 clock-names = "clkout16";
924 clocks = <&clock CLK_FIN_PLL>;
925 #clock-cells = <1>;
926 interrupt-controller;
927 #interrupt-cells = <3>;
928 interrupt-parent = <&gic>;
930 dp_phy: dp-phy {
931 compatible = "samsung,exynos5420-dp-video-phy";
932 #phy-cells = <0>;
935 mipi_phy: mipi-phy {
936 compatible = "samsung,exynos5420-mipi-video-phy";
937 #phy-cells = <1>;
942 compatible = "samsung,exynos5420-tmu";
945 clocks = <&clock CLK_TMU>;
946 clock-names = "tmu_apbif";
947 #thermal-sensor-cells = <0>;
951 compatible = "samsung,exynos5420-tmu";
954 clocks = <&clock CLK_TMU>;
955 clock-names = "tmu_apbif";
956 #thermal-sensor-cells = <0>;
960 compatible = "samsung,exynos5420-tmu-ext-triminfo";
963 clocks = <&clock CLK_TMU>, <&clock CLK_TMU>;
964 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
965 #thermal-sensor-cells = <0>;
969 compatible = "samsung,exynos5420-tmu-ext-triminfo";
972 clocks = <&clock CLK_TMU>, <&clock CLK_TMU_GPU>;
973 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
974 #thermal-sensor-cells = <0>;
978 compatible = "samsung,exynos5420-tmu-ext-triminfo";
981 clocks = <&clock CLK_TMU_GPU>, <&clock CLK_TMU>;
982 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
983 #thermal-sensor-cells = <0>;
987 compatible = "samsung,exynos-sysmmu";
989 interrupt-parent = <&combiner>;
991 clock-names = "sysmmu", "master";
992 clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
993 #iommu-cells = <0>;
997 compatible = "samsung,exynos-sysmmu";
999 interrupt-parent = <&combiner>;
1001 clock-names = "sysmmu", "master";
1002 clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
1003 #iommu-cells = <0>;
1007 compatible = "samsung,exynos-sysmmu";
1009 interrupt-parent = <&combiner>;
1011 clock-names = "sysmmu", "master";
1012 clocks = <&clock CLK_SMMU_MIXER>, <&clock CLK_MIXER>;
1013 power-domains = <&disp_pd>;
1014 #iommu-cells = <0>;
1018 compatible = "samsung,exynos-sysmmu";
1020 interrupt-parent = <&combiner>;
1022 clock-names = "sysmmu", "master";
1023 clocks = <&clock CLK_SMMU_GSCL0>, <&clock CLK_GSCL0>;
1024 power-domains = <&gsc_pd>;
1025 #iommu-cells = <0>;
1029 compatible = "samsung,exynos-sysmmu";
1031 interrupt-parent = <&combiner>;
1033 clock-names = "sysmmu", "master";
1034 clocks = <&clock CLK_SMMU_GSCL1>, <&clock CLK_GSCL1>;
1035 power-domains = <&gsc_pd>;
1036 #iommu-cells = <0>;
1040 compatible = "samsung,exynos-sysmmu";
1042 interrupt-parent = <&combiner>;
1044 clock-names = "sysmmu", "master";
1045 clocks = <&clock CLK_SMMU_MSCL0>, <&clock CLK_MSCL0>;
1046 power-domains = <&msc_pd>;
1047 #iommu-cells = <0>;
1051 compatible = "samsung,exynos-sysmmu";
1054 clock-names = "sysmmu", "master";
1055 clocks = <&clock CLK_SMMU_MSCL1>, <&clock CLK_MSCL1>;
1056 power-domains = <&msc_pd>;
1057 #iommu-cells = <0>;
1061 compatible = "samsung,exynos-sysmmu";
1064 clock-names = "sysmmu", "master";
1065 clocks = <&clock CLK_SMMU_MSCL2>, <&clock CLK_MSCL2>;
1066 power-domains = <&msc_pd>;
1067 #iommu-cells = <0>;
1071 compatible = "samsung,exynos-sysmmu";
1073 interrupt-parent = <&combiner>;
1075 clock-names = "sysmmu", "master";
1076 clocks = <&clock CLK_SMMU_MSCL0>, <&clock CLK_MSCL0>;
1077 power-domains = <&msc_pd>;
1078 #iommu-cells = <0>;
1082 compatible = "samsung,exynos-sysmmu";
1084 interrupt-parent = <&combiner>;
1086 clock-names = "sysmmu", "master";
1087 clocks = <&clock CLK_SMMU_MSCL1>, <&clock CLK_MSCL1>;
1088 power-domains = <&msc_pd>;
1089 #iommu-cells = <0>;
1093 compatible = "samsung,exynos-sysmmu";
1095 interrupt-parent = <&combiner>;
1097 clock-names = "sysmmu", "master";
1098 clocks = <&clock CLK_SMMU_MSCL2>, <&clock CLK_MSCL2>;
1099 power-domains = <&msc_pd>;
1100 #iommu-cells = <0>;
1104 compatible = "samsung,exynos-sysmmu";
1106 interrupt-parent = <&combiner>;
1108 clock-names = "sysmmu", "master";
1109 clocks = <&clock CLK_SMMU_ROTATOR>, <&clock CLK_ROTATOR>;
1110 #iommu-cells = <0>;
1114 compatible = "samsung,exynos-sysmmu";
1116 interrupt-parent = <&combiner>;
1118 clock-names = "sysmmu", "master";
1119 clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>;
1120 #iommu-cells = <0>;
1124 compatible = "samsung,exynos-sysmmu";
1127 clock-names = "sysmmu", "master";
1128 clocks = <&clock CLK_SMMU_JPEG2>, <&clock CLK_JPEG2>;
1129 #iommu-cells = <0>;
1133 compatible = "samsung,exynos-sysmmu";
1135 interrupt-parent = <&combiner>;
1137 clock-names = "sysmmu", "master";
1138 clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>;
1139 power-domains = <&mfc_pd>;
1140 #iommu-cells = <0>;
1144 compatible = "samsung,exynos-sysmmu";
1146 interrupt-parent = <&combiner>;
1148 clock-names = "sysmmu", "master";
1149 clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>;
1150 power-domains = <&mfc_pd>;
1151 #iommu-cells = <0>;
1155 compatible = "samsung,exynos-sysmmu";
1157 interrupt-parent = <&combiner>;
1159 clock-names = "sysmmu", "master";
1160 clocks = <&clock CLK_SMMU_FIMD1M0>, <&clock CLK_FIMD1>;
1161 power-domains = <&disp_pd>;
1162 #iommu-cells = <0>;
1166 compatible = "samsung,exynos-sysmmu";
1168 interrupt-parent = <&combiner>;
1170 clock-names = "sysmmu", "master";
1171 clocks = <&clock CLK_SMMU_FIMD1M1>, <&clock CLK_FIMD1>;
1172 power-domains = <&disp_pd>;
1173 #iommu-cells = <0>;
1177 thermal-zones {
1178 cpu0_thermal: cpu0-thermal {
1179 thermal-sensors = <&tmu_cpu0>;
1180 #include "exynos5420-trip-points.dtsi"
1182 cpu1_thermal: cpu1-thermal {
1183 thermal-sensors = <&tmu_cpu1>;
1184 #include "exynos5420-trip-points.dtsi"
1186 cpu2_thermal: cpu2-thermal {
1187 thermal-sensors = <&tmu_cpu2>;
1188 #include "exynos5420-trip-points.dtsi"
1190 cpu3_thermal: cpu3-thermal {
1191 thermal-sensors = <&tmu_cpu3>;
1192 #include "exynos5420-trip-points.dtsi"
1194 gpu_thermal: gpu-thermal {
1195 thermal-sensors = <&tmu_gpu>;
1196 #include "exynos5420-trip-points.dtsi"
1202 clocks = <&clock CLK_TSADC>;
1203 clock-names = "adc";
1204 samsung,syscon-phandle = <&pmu_system_controller>;
1208 clocks = <&clock CLK_DP1>;
1209 clock-names = "dp";
1211 phy-names = "dp";
1212 power-domains = <&disp_pd>;
1216 compatible = "samsung,exynos5420-fimd";
1217 clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
1218 clock-names = "sclk_fimd", "fimd";
1219 power-domains = <&disp_pd>;
1221 iommu-names = "m0", "m1";
1226 clocks = <&clock CLK_G2D>;
1227 clock-names = "fimg2d";
1232 clocks = <&clock CLK_I2C0>;
1233 clock-names = "i2c";
1234 pinctrl-names = "default";
1235 pinctrl-0 = <&i2c0_bus>;
1239 clocks = <&clock CLK_I2C1>;
1240 clock-names = "i2c";
1241 pinctrl-names = "default";
1242 pinctrl-0 = <&i2c1_bus>;
1246 clocks = <&clock CLK_I2C2>;
1247 clock-names = "i2c";
1248 pinctrl-names = "default";
1249 pinctrl-0 = <&i2c2_bus>;
1253 clocks = <&clock CLK_I2C3>;
1254 clock-names = "i2c";
1255 pinctrl-names = "default";
1256 pinctrl-0 = <&i2c3_bus>;
1260 clocks = <&clock CLK_USI0>;
1261 clock-names = "hsi2c";
1262 pinctrl-names = "default";
1263 pinctrl-0 = <&i2c4_hs_bus>;
1267 clocks = <&clock CLK_USI1>;
1268 clock-names = "hsi2c";
1269 pinctrl-names = "default";
1270 pinctrl-0 = <&i2c5_hs_bus>;
1274 clocks = <&clock CLK_USI2>;
1275 clock-names = "hsi2c";
1276 pinctrl-names = "default";
1277 pinctrl-0 = <&i2c6_hs_bus>;
1281 clocks = <&clock CLK_USI3>;
1282 clock-names = "hsi2c";
1283 pinctrl-names = "default";
1284 pinctrl-0 = <&i2c7_hs_bus>;
1288 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
1289 clock-names = "fin_pll", "mct";
1293 clocks = <&clock CLK_SSS>;
1294 clock-names = "secss";
1298 clocks = <&clock CLK_PWM>;
1299 clock-names = "timers";
1303 clocks = <&clock CLK_RTC>;
1304 clock-names = "rtc";
1305 interrupt-parent = <&pmu_system_controller>;
1310 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
1311 clock-names = "uart", "clk_uart_baud0";
1313 dma-names = "rx", "tx";
1317 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
1318 clock-names = "uart", "clk_uart_baud0";
1320 dma-names = "rx", "tx";
1324 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
1325 clock-names = "uart", "clk_uart_baud0";
1327 dma-names = "rx", "tx";
1331 clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
1332 clock-names = "uart", "clk_uart_baud0";
1334 dma-names = "rx", "tx";
1338 clocks = <&clock CLK_SSS>;
1339 clock-names = "secss";
1343 clocks = <&clock CLK_SSS>;
1344 clock-names = "secss";
1348 clocks = <&clock CLK_USBD300>;
1349 clock-names = "usbdrd30";
1353 clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>;
1354 clock-names = "phy", "ref";
1355 samsung,pmu-syscon = <&pmu_system_controller>;
1359 clocks = <&clock CLK_USBD301>;
1360 clock-names = "usbdrd30";
1368 clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBPHY301>;
1369 clock-names = "phy", "ref";
1370 samsung,pmu-syscon = <&pmu_system_controller>;
1374 clocks = <&clock CLK_USBH20>;
1375 clock-names = "usbhost";
1379 clocks = <&clock CLK_USBH20>;
1380 clock-names = "usbhost";
1384 clocks = <&clock CLK_USBH20>, <&clock CLK_SCLK_USBPHY300>;
1385 clock-names = "phy", "ref";
1386 samsung,sysreg-phandle = <&sysreg_system_controller>;
1387 samsung,pmureg-phandle = <&pmu_system_controller>;
1391 clocks = <&clock CLK_WDT>;
1392 clock-names = "watchdog";
1393 samsung,syscon-phandle = <&pmu_system_controller>;
1396 #include "exynos5420-pinctrl.dtsi"
1397 #include "exynos-syscon-restart.dtsi"