Lines Matching +full:0 +full:x10700000
35 #size-cells = <0>;
63 cpu0: cpu@0 {
66 reg = <0x0>;
73 reg = <0x1>;
80 reg = <0x100>;
87 reg = <0x101>;
94 reg = <0x102>;
101 reg = <0x103>;
114 reg = <0x10010000 0x10000>;
128 reg = <0x10200000 0x10000>;
160 reg = <0x10600000 0x10000>;
170 reg = <0x10700000 0x10000>;
180 reg = <0x10a00000 0x10000>;
190 reg = <0x10ce0000 0x10000>;
198 reg = <0x11090000 0x10000>;
208 reg = <0x11830000 0x10000>;
216 reg = <0x122e0000 0x10000>;
236 reg = <0x128c0000 0x10000>;
250 reg = <0x133c0000 0x10000>;
264 reg = <0x13f00000 0x10000>;
276 reg = <0x14550000 0x10000>;
322 reg = <0x10481000 0x1000>,
323 <0x10482000 0x2000>,
324 <0x10484000 0x2000>,
325 <0x10486000 0x2000>;
332 reg = <0x10000000 0x100>;
338 reg = <0x100b0000 0x1000>;
359 reg = <0x10f00000 0x1000>;
360 ranges = <0x0 0x10f00000 0x6000>;
365 reg = <0x4000 0x1000>;
371 reg = <0x5000 0x1000>;
377 reg = <0x11600000 0x1000>;
389 reg = <0x12290000 0x1000>;
395 reg = <0x128b0000 0x1000>;
401 reg = <0x10d50000 0x10000>;
406 reg = <0x12c00000 0x100>;
415 reg = <0x12c10000 0x100>;
424 reg = <0x12c20000 0x100>;
433 reg = <0x12860000 0x100>;
442 reg = <0x12140000 0x2000>;
445 #size-cells = <0>;
455 assigned-clock-rates = <0>, <0>, <800000000>;
462 reg = <0x12150000 0x2000>;
465 #size-cells = <0>;
475 assigned-clock-rates = <0>, <0>, <800000000>;
482 reg = <0x12160000 0x2000>;
485 #size-cells = <0>;
495 assigned-clock-rates = <0>, <0>, <800000000>;
502 reg = <0x12da0000 0x1000>;
505 #size-cells = <0>;
507 pinctrl-0 = <&i2c0_hs_bus>;
515 reg = <0x12db0000 0x1000>;
518 #size-cells = <0>;
520 pinctrl-0 = <&i2c1_hs_bus>;
528 reg = <0x12dc0000 0x1000>;
531 #size-cells = <0>;
533 pinctrl-0 = <&i2c2_hs_bus>;
541 reg = <0x12dd0000 0x1000>;
544 #size-cells = <0>;
546 pinctrl-0 = <&i2c3_hs_bus>;