Lines Matching +full:axi +full:- +full:adc
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rockchip,rv1126-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rockchip,rv1126-power.h>
12 #include <dt-bindings/soc/rockchip,boot-mode.h>
15 #address-cells = <1>;
16 #size-cells = <1>;
20 interrupt-parent = <&gic>;
34 #address-cells = <1>;
35 #size-cells = <0>;
39 compatible = "arm,cortex-a7";
41 enable-method = "psci";
47 compatible = "arm,cortex-a7";
49 enable-method = "psci";
55 compatible = "arm,cortex-a7";
57 enable-method = "psci";
63 compatible = "arm,cortex-a7";
65 enable-method = "psci";
70 arm-pmu {
71 compatible = "arm,cortex-a7-pmu";
76 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
80 compatible = "arm,psci-1.0";
85 compatible = "arm,armv7-timer";
90 clock-frequency = <24000000>;
94 compatible = "rockchip,display-subsystem";
99 compatible = "fixed-clock";
100 clock-frequency = <24000000>;
101 clock-output-names = "xin24m";
102 #clock-cells = <0>;
106 compatible = "rockchip,rv1126-grf", "syscon", "simple-mfd";
111 compatible = "rockchip,rv1126-pmugrf", "syscon", "simple-mfd";
114 pmu_io_domains: io-domains {
115 compatible = "rockchip,rv1126-pmu-io-voltage-domain";
121 compatible = "rockchip,rv1126-qos", "syscon";
126 compatible = "rockchip,rv1126-qos", "syscon";
131 compatible = "rockchip,rv1126-qos", "syscon";
136 compatible = "rockchip,rv1126-qos", "syscon";
141 compatible = "rockchip,rv1126-qos", "syscon";
146 compatible = "rockchip,rv1126-qos", "syscon";
151 compatible = "rockchip,rv1126-qos", "syscon";
156 compatible = "rockchip,rv1126-qos", "syscon";
160 gic: interrupt-controller@feff0000 {
161 compatible = "arm,gic-400";
162 interrupt-controller;
163 #interrupt-cells = <3>;
164 #address-cells = <0>;
173 pmu: power-management@ff3e0000 {
174 compatible = "rockchip,rv1126-pmu", "syscon", "simple-mfd";
177 power: power-controller {
178 compatible = "rockchip,rv1126-power-controller";
179 #power-domain-cells = <1>;
180 #address-cells = <1>;
181 #size-cells = <0>;
183 power-domain@RV1126_PD_NVM {
195 #power-domain-cells = <0>;
198 power-domain@RV1126_PD_SDIO {
203 #power-domain-cells = <0>;
206 power-domain@RV1126_PD_VO {
222 #power-domain-cells = <0>;
228 compatible = "rockchip,rv1126-i2c", "rockchip,rk3399-i2c";
233 clock-names = "i2c", "pclk";
234 pinctrl-names = "default";
235 pinctrl-0 = <&i2c0_xfer>;
236 #address-cells = <1>;
237 #size-cells = <0>;
242 compatible = "rockchip,rv1126-i2c", "rockchip,rk3399-i2c";
247 clock-names = "i2c", "pclk";
248 pinctrl-names = "default";
249 pinctrl-0 = <&i2c2_xfer>;
250 #address-cells = <1>;
251 #size-cells = <0>;
256 compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
259 clock-frequency = <24000000>;
261 clock-names = "baudclk", "apb_pclk";
263 dma-names = "tx", "rx";
264 pinctrl-names = "default";
265 pinctrl-0 = <&uart1m0_xfer>;
266 reg-shift = <2>;
267 reg-io-width = <4>;
272 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm";
274 clock-names = "pwm", "pclk";
276 pinctrl-names = "default";
277 pinctrl-0 = <&pwm2m0_pins>;
278 #pwm-cells = <3>;
282 pmucru: clock-controller@ff480000 {
283 compatible = "rockchip,rv1126-pmucru";
286 #clock-cells = <1>;
287 #reset-cells = <1>;
290 cru: clock-controller@ff490000 {
291 compatible = "rockchip,rv1126-cru";
294 clock-names = "xin24m";
296 #clock-cells = <1>;
297 #reset-cells = <1>;
300 dmac: dma-controller@ff4e0000 {
305 #dma-cells = <1>;
306 arm,pl330-periph-burst;
308 clock-names = "apb_pclk";
312 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm";
314 clock-names = "pwm", "pclk";
316 pinctrl-0 = <&pwm11m0_pins>;
317 pinctrl-names = "default";
318 #pwm-cells = <3>;
323 compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
326 clock-frequency = <24000000>;
328 clock-names = "baudclk", "apb_pclk";
330 dma-names = "tx", "rx";
331 pinctrl-names = "default";
332 pinctrl-0 = <&uart0_xfer>;
333 reg-shift = <2>;
334 reg-io-width = <4>;
339 compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
342 clock-frequency = <24000000>;
344 clock-names = "baudclk", "apb_pclk";
346 dma-names = "tx", "rx";
347 pinctrl-names = "default";
348 pinctrl-0 = <&uart2m1_xfer>;
349 reg-shift = <2>;
350 reg-io-width = <4>;
355 compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
358 clock-frequency = <24000000>;
360 clock-names = "baudclk", "apb_pclk";
362 dma-names = "tx", "rx";
363 pinctrl-names = "default";
364 pinctrl-0 = <&uart3m0_xfer>;
365 reg-shift = <2>;
366 reg-io-width = <4>;
371 compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
374 clock-frequency = <24000000>;
376 clock-names = "baudclk", "apb_pclk";
378 dma-names = "tx", "rx";
379 pinctrl-names = "default";
380 pinctrl-0 = <&uart4m0_xfer>;
381 reg-shift = <2>;
382 reg-io-width = <4>;
387 compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
390 clock-frequency = <24000000>;
392 clock-names = "baudclk", "apb_pclk";
394 dma-names = "tx", "rx";
395 pinctrl-names = "default";
396 pinctrl-0 = <&uart5m0_xfer>;
397 reg-shift = <2>;
398 reg-io-width = <4>;
402 saradc: adc@ff5e0000 {
403 compatible = "rockchip,rv1126-saradc", "rockchip,rk3399-saradc";
406 #io-channel-cells = <1>;
408 clock-names = "saradc", "apb_pclk";
410 reset-names = "saradc-apb";
415 compatible = "rockchip,rv1126-timer", "rockchip,rk3288-timer";
419 clock-names = "pclk", "timer";
423 compatible = "rockchip,rv1126-vop";
426 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
428 reset-names = "axi", "ahb", "dclk";
431 power-domains = <&power RV1126_PD_VO>;
435 #address-cells = <1>;
436 #size-cells = <0>;
452 clock-names = "aclk", "iface";
454 #iommu-cells = <0>;
455 power-domains = <&power RV1126_PD_VO>;
460 compatible = "rockchip,rv1126-gmac", "snps,dwmac-4.20a";
464 interrupt-names = "macirq", "eth_wake_irq";
470 clock-names = "stmmaceth", "mac_clk_rx",
475 reset-names = "stmmaceth";
477 snps,mixed-burst;
480 snps,axi-config = <&stmmac_axi_setup>;
481 snps,mtl-rx-config = <&mtl_rx_setup>;
482 snps,mtl-tx-config = <&mtl_tx_setup>;
486 compatible = "snps,dwmac-mdio";
487 #address-cells = <0x1>;
488 #size-cells = <0x0>;
491 stmmac_axi_setup: stmmac-axi-config {
497 mtl_rx_setup: rx-queues-config {
498 snps,rx-queues-to-use = <1>;
502 mtl_tx_setup: tx-queues-config {
503 snps,tx-queues-to-use = <1>;
509 compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc";
514 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
515 fifo-depth = <0x100>;
516 max-frequency = <200000000>;
517 power-domains = <&power RV1126_PD_NVM>;
522 compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc";
527 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
528 fifo-depth = <0x100>;
529 max-frequency = <200000000>;
534 compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc";
539 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
540 fifo-depth = <0x100>;
541 max-frequency = <200000000>;
542 power-domains = <&power RV1126_PD_SDIO>;
550 assigned-clocks = <&cru SCLK_SFC>;
551 assigned-clock-rates = <80000000>;
552 clock-names = "clk_sfc", "hclk_sfc";
554 power-domains = <&power RV1126_PD_NVM>;
559 compatible = "rockchip,rv1126-pinctrl";
562 #address-cells = <1>;
563 #size-cells = <1>;
567 compatible = "rockchip,gpio-bank";
571 gpio-controller;
572 #gpio-cells = <2>;
573 interrupt-controller;
574 #interrupt-cells = <2>;
578 compatible = "rockchip,gpio-bank";
582 gpio-controller;
583 #gpio-cells = <2>;
584 interrupt-controller;
585 #interrupt-cells = <2>;
589 compatible = "rockchip,gpio-bank";
593 gpio-controller;
594 #gpio-cells = <2>;
595 interrupt-controller;
596 #interrupt-cells = <2>;
600 compatible = "rockchip,gpio-bank";
604 gpio-controller;
605 #gpio-cells = <2>;
606 interrupt-controller;
607 #interrupt-cells = <2>;
611 compatible = "rockchip,gpio-bank";
615 gpio-controller;
616 #gpio-cells = <2>;
617 interrupt-controller;
618 #interrupt-cells = <2>;
623 #include "rv1126-pinctrl.dtsi"