Lines Matching +full:0 +full:x10240000
29 #size-cells = <0>;
34 reg = <0xf00>;
43 cpu_opp_table: opp-table-0 {
85 #clock-cells = <0>;
90 reg = <0x10080000 0x2000>;
93 ranges = <0 0x10080000 0x2000>;
98 reg = <0x10210000 0x100>;
107 pinctrl-0 = <&uart2m0_xfer>;
113 reg = <0x10220000 0x100>;
122 pinctrl-0 = <&uart1_xfer>;
128 reg = <0x10230000 0x100>;
137 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
143 reg = <0x10240000 0x1000>;
146 #size-cells = <0>;
150 pinctrl-0 = <&i2c1_xfer>;
157 reg = <0x10250000 0x1000>;
160 #size-cells = <0>;
164 pinctrl-0 = <&i2c2m1_xfer>;
171 reg = <0x10260000 0x1000>;
174 #size-cells = <0>;
178 pinctrl-0 = <&i2c3_xfer>;
185 reg = <0x10270000 0x1000>;
192 #size-cells = <0>;
198 reg = <0x10280000 0x10>;
202 pinctrl-0 = <&pwm4_pin>;
209 reg = <0x10280010 0x10>;
213 pinctrl-0 = <&pwm5_pin>;
220 reg = <0x10280020 0x10>;
224 pinctrl-0 = <&pwm6_pin>;
231 reg = <0x10280030 0x10>;
235 pinctrl-0 = <&pwm7_pin>;
242 reg = <0x102a0000 0x4000>;
243 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
253 reg = <0x10300000 0x1000>;
264 reg = <0x100 0x0c>;
267 #clock-cells = <0>;
275 #phy-cells = <0>;
282 #phy-cells = <0>;
290 reg = <0x10350000 0x20>;
298 reg = <0x10360000 0x100>;
309 thermal-sensors = <&tsadc 0>;
341 reg = <0x10370000 0x100>;
348 pinctrl-0 = <&otp_pin>;
360 reg = <0x1038c000 0x100>;
370 reg = <0x20000000 0x1000>;
373 #size-cells = <0>;
377 pinctrl-0 = <&i2c0_xfer>;
384 reg = <0x20040000 0x10>;
388 pinctrl-0 = <&pwm0_pin>;
395 reg = <0x20040010 0x10>;
399 pinctrl-0 = <&pwm1_pin>;
406 reg = <0x20040020 0x10>;
410 pinctrl-0 = <&pwm2_pin>;
417 reg = <0x20040030 0x10>;
421 pinctrl-0 = <&pwm3_pin>;
428 reg = <0x20060000 0x1000>;
438 reg = <0x202a0000 0x1000>;
443 reg = <0x20200000 0x1000>;
453 reg = <0x30100000 0x1000>;
464 reg = <0x30110000 0x4000>;
469 fifo-depth = <0x100>;
476 reg = <0x30120000 0x4000>;
481 fifo-depth = <0x100>;
488 reg = <0x30130000 0x4000>;
493 fifo-depth = <0x100>;
496 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
502 reg = <0x30140000 0x20000>;
512 reg = <0x30160000 0x20000>;
523 reg = <0x30180000 0x40000>;
538 reg = <0x301c0000 0x4000>;
542 pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus4>;
549 reg = <0x30200000 0x10000>;
564 pinctrl-0 = <&rmii_pins>;
573 #address-cells = <0>;
575 reg = <0x32011000 0x1000>,
576 <0x32012000 0x2000>,
577 <0x32014000 0x2000>,
578 <0x32016000 0x2000>;
592 reg = <0x20030000 0x100>;
605 reg = <0x10310000 0x100>;
618 reg = <0x10320000 0x100>;
631 reg = <0x10330000 0x100>;
758 rockchip,pins = <0 RK_PB1 1 &pcfg_pull_none_smt>,
759 <0 RK_PB2 1 &pcfg_pull_none_smt>;
772 rockchip,pins = <0 RK_PC2 2 &pcfg_pull_none>,
773 <0 RK_PC6 3 &pcfg_pull_none>;
777 rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>,
778 <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
796 rockchip,pins = <0 RK_PB6 1 &pcfg_pull_none>,
797 <0 RK_PC4 2 &pcfg_pull_none>;
803 rockchip,pins = <0 RK_PC5 1 &pcfg_pull_none>;
809 rockchip,pins = <0 RK_PC4 1 &pcfg_pull_none>;
815 rockchip,pins = <0 RK_PC6 1 &pcfg_pull_none>;
821 rockchip,pins = <0 RK_PC0 1 &pcfg_pull_none>;
859 rockchip,pins = <0 RK_PA1 1 &pcfg_pull_up_drv_4ma>;
894 rockchip,pins = <0 RK_PA3 1 &pcfg_pull_up>;
898 rockchip,pins = <0 RK_PA4 1 &pcfg_pull_up>;
902 rockchip,pins = <0 RK_PB0 1 &pcfg_pull_up>;
906 rockchip,pins = <0 RK_PA7 1 &pcfg_pull_up>;
912 rockchip,pins = <0 RK_PB7 1 &pcfg_pull_none>;
916 rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;