Lines Matching +full:rk3288 +full:- +full:cru
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include <dt-bindings/clock/rk3288-cru.h>
8 #include <dt-bindings/power/rk3288-power.h>
9 #include <dt-bindings/thermal/thermal.h>
10 #include <dt-bindings/soc/rockchip,boot-mode.h>
13 #address-cells = <2>;
14 #size-cells = <2>;
16 compatible = "rockchip,rk3288";
18 interrupt-parent = <&gic>;
51 arm-pmu {
52 compatible = "arm,cortex-a12-pmu";
57 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
61 #address-cells = <1>;
62 #size-cells = <0>;
63 enable-method = "rockchip,rk3066-smp";
68 compatible = "arm,cortex-a12";
70 resets = <&cru SRST_CORE0>;
71 operating-points-v2 = <&cpu_opp_table>;
72 #cooling-cells = <2>; /* min followed by max */
73 clock-latency = <40000>;
74 clocks = <&cru ARMCLK>;
75 dynamic-power-coefficient = <370>;
79 compatible = "arm,cortex-a12";
81 resets = <&cru SRST_CORE1>;
82 operating-points-v2 = <&cpu_opp_table>;
83 #cooling-cells = <2>; /* min followed by max */
84 clock-latency = <40000>;
85 clocks = <&cru ARMCLK>;
86 dynamic-power-coefficient = <370>;
90 compatible = "arm,cortex-a12";
92 resets = <&cru SRST_CORE2>;
93 operating-points-v2 = <&cpu_opp_table>;
94 #cooling-cells = <2>; /* min followed by max */
95 clock-latency = <40000>;
96 clocks = <&cru ARMCLK>;
97 dynamic-power-coefficient = <370>;
101 compatible = "arm,cortex-a12";
103 resets = <&cru SRST_CORE3>;
104 operating-points-v2 = <&cpu_opp_table>;
105 #cooling-cells = <2>; /* min followed by max */
106 clock-latency = <40000>;
107 clocks = <&cru ARMCLK>;
108 dynamic-power-coefficient = <370>;
112 cpu_opp_table: opp-table-0 {
113 compatible = "operating-points-v2";
114 opp-shared;
116 opp-126000000 {
117 opp-hz = /bits/ 64 <126000000>;
118 opp-microvolt = <900000>;
120 opp-216000000 {
121 opp-hz = /bits/ 64 <216000000>;
122 opp-microvolt = <900000>;
124 opp-312000000 {
125 opp-hz = /bits/ 64 <312000000>;
126 opp-microvolt = <900000>;
128 opp-408000000 {
129 opp-hz = /bits/ 64 <408000000>;
130 opp-microvolt = <900000>;
132 opp-600000000 {
133 opp-hz = /bits/ 64 <600000000>;
134 opp-microvolt = <900000>;
136 opp-696000000 {
137 opp-hz = /bits/ 64 <696000000>;
138 opp-microvolt = <950000>;
140 opp-816000000 {
141 opp-hz = /bits/ 64 <816000000>;
142 opp-microvolt = <1000000>;
144 opp-1008000000 {
145 opp-hz = /bits/ 64 <1008000000>;
146 opp-microvolt = <1050000>;
148 opp-1200000000 {
149 opp-hz = /bits/ 64 <1200000000>;
150 opp-microvolt = <1100000>;
152 opp-1416000000 {
153 opp-hz = /bits/ 64 <1416000000>;
154 opp-microvolt = <1200000>;
156 opp-1512000000 {
157 opp-hz = /bits/ 64 <1512000000>;
158 opp-microvolt = <1300000>;
160 opp-1608000000 {
161 opp-hz = /bits/ 64 <1608000000>;
162 opp-microvolt = <1350000>;
166 reserved-memory {
167 #address-cells = <2>;
168 #size-cells = <2>;
172 * The rk3288 cannot use the memory area above 0xfe000000
181 dma-unusable@fe000000 {
187 compatible = "fixed-clock";
188 clock-frequency = <24000000>;
189 clock-output-names = "xin24m";
190 #clock-cells = <0>;
194 compatible = "arm,armv7-timer";
195 arm,cpu-registers-not-fw-configured;
200 clock-frequency = <24000000>;
201 arm,no-tick-in-suspend;
205 compatible = "rockchip,rk3288-timer";
208 clocks = <&cru PCLK_TIMER>, <&xin24m>;
209 clock-names = "pclk", "timer";
212 display-subsystem {
213 compatible = "rockchip,display-subsystem";
218 compatible = "rockchip,rk3288-dw-mshc";
219 max-frequency = <150000000>;
220 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
221 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
222 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
223 fifo-depth = <0x100>;
226 resets = <&cru SRST_MMC0>;
227 reset-names = "reset";
232 compatible = "rockchip,rk3288-dw-mshc";
233 max-frequency = <150000000>;
234 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
235 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
236 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
237 fifo-depth = <0x100>;
240 resets = <&cru SRST_SDIO0>;
241 reset-names = "reset";
246 compatible = "rockchip,rk3288-dw-mshc";
247 max-frequency = <150000000>;
248 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>,
249 <&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>;
250 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
251 fifo-depth = <0x100>;
254 resets = <&cru SRST_SDIO1>;
255 reset-names = "reset";
260 compatible = "rockchip,rk3288-dw-mshc";
261 max-frequency = <150000000>;
262 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
263 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
264 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
265 fifo-depth = <0x100>;
268 resets = <&cru SRST_EMMC>;
269 reset-names = "reset";
277 #io-channel-cells = <1>;
278 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
279 clock-names = "saradc", "apb_pclk";
280 resets = <&cru SRST_SARADC>;
281 reset-names = "saradc-apb";
286 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
287 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
288 clock-names = "spiclk", "apb_pclk";
290 dma-names = "tx", "rx";
292 pinctrl-names = "default";
293 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
295 #address-cells = <1>;
296 #size-cells = <0>;
301 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
302 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
303 clock-names = "spiclk", "apb_pclk";
305 dma-names = "tx", "rx";
307 pinctrl-names = "default";
308 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
310 #address-cells = <1>;
311 #size-cells = <0>;
316 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
317 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
318 clock-names = "spiclk", "apb_pclk";
320 dma-names = "tx", "rx";
322 pinctrl-names = "default";
323 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
325 #address-cells = <1>;
326 #size-cells = <0>;
331 compatible = "rockchip,rk3288-i2c";
334 #address-cells = <1>;
335 #size-cells = <0>;
336 clock-names = "i2c";
337 clocks = <&cru PCLK_I2C1>;
338 pinctrl-names = "default";
339 pinctrl-0 = <&i2c1_xfer>;
344 compatible = "rockchip,rk3288-i2c";
347 #address-cells = <1>;
348 #size-cells = <0>;
349 clock-names = "i2c";
350 clocks = <&cru PCLK_I2C3>;
351 pinctrl-names = "default";
352 pinctrl-0 = <&i2c3_xfer>;
357 compatible = "rockchip,rk3288-i2c";
360 #address-cells = <1>;
361 #size-cells = <0>;
362 clock-names = "i2c";
363 clocks = <&cru PCLK_I2C4>;
364 pinctrl-names = "default";
365 pinctrl-0 = <&i2c4_xfer>;
370 compatible = "rockchip,rk3288-i2c";
373 #address-cells = <1>;
374 #size-cells = <0>;
375 clock-names = "i2c";
376 clocks = <&cru PCLK_I2C5>;
377 pinctrl-names = "default";
378 pinctrl-0 = <&i2c5_xfer>;
383 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
386 reg-shift = <2>;
387 reg-io-width = <4>;
388 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
389 clock-names = "baudclk", "apb_pclk";
391 dma-names = "tx", "rx";
392 pinctrl-names = "default";
393 pinctrl-0 = <&uart0_xfer>;
398 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
401 reg-shift = <2>;
402 reg-io-width = <4>;
403 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
404 clock-names = "baudclk", "apb_pclk";
406 dma-names = "tx", "rx";
407 pinctrl-names = "default";
408 pinctrl-0 = <&uart1_xfer>;
413 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
416 reg-shift = <2>;
417 reg-io-width = <4>;
418 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
419 clock-names = "baudclk", "apb_pclk";
420 pinctrl-names = "default";
421 pinctrl-0 = <&uart2_xfer>;
426 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
429 reg-shift = <2>;
430 reg-io-width = <4>;
431 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
432 clock-names = "baudclk", "apb_pclk";
434 dma-names = "tx", "rx";
435 pinctrl-names = "default";
436 pinctrl-0 = <&uart3_xfer>;
441 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
444 reg-shift = <2>;
445 reg-io-width = <4>;
446 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
447 clock-names = "baudclk", "apb_pclk";
449 dma-names = "tx", "rx";
450 pinctrl-names = "default";
451 pinctrl-0 = <&uart4_xfer>;
455 dmac_peri: dma-controller@ff250000 {
460 #dma-cells = <1>;
461 arm,pl330-broken-no-flushp;
462 arm,pl330-periph-burst;
463 clocks = <&cru ACLK_DMAC2>;
464 clock-names = "apb_pclk";
467 thermal-zones {
468 reserve_thermal: reserve-thermal {
469 polling-delay-passive = <1000>; /* milliseconds */
470 polling-delay = <5000>; /* milliseconds */
472 thermal-sensors = <&tsadc 0>;
475 cpu_thermal: cpu-thermal {
476 polling-delay-passive = <100>; /* milliseconds */
477 polling-delay = <5000>; /* milliseconds */
479 thermal-sensors = <&tsadc 1>;
499 cooling-maps {
502 cooling-device =
510 cooling-device =
519 gpu_thermal: gpu-thermal {
520 polling-delay-passive = <100>; /* milliseconds */
521 polling-delay = <5000>; /* milliseconds */
523 thermal-sensors = <&tsadc 2>;
538 cooling-maps {
541 cooling-device =
549 compatible = "rockchip,rk3288-tsadc";
552 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
553 clock-names = "tsadc", "apb_pclk";
554 resets = <&cru SRST_TSADC>;
555 reset-names = "tsadc-apb";
556 pinctrl-names = "init", "default", "sleep";
557 pinctrl-0 = <&otp_pin>;
558 pinctrl-1 = <&otp_out>;
559 pinctrl-2 = <&otp_pin>;
560 #thermal-sensor-cells = <1>;
562 rockchip,hw-tshut-temp = <95000>;
567 compatible = "rockchip,rk3288-gmac";
571 interrupt-names = "macirq", "eth_wake_irq";
573 clocks = <&cru SCLK_MAC>,
574 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
575 <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
576 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
577 clock-names = "stmmaceth",
581 resets = <&cru SRST_MAC>;
582 reset-names = "stmmaceth";
587 compatible = "generic-ehci";
590 clocks = <&cru HCLK_USBHOST0>;
592 phy-names = "usb";
596 /* NOTE: doesn't work on RK3288, but was fixed on RK3288W */
598 compatible = "generic-ohci";
601 clocks = <&cru HCLK_USBHOST0>;
603 phy-names = "usb";
608 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
612 clocks = <&cru HCLK_USBHOST1>;
613 clock-names = "otg";
616 phy-names = "usb2-phy";
617 snps,reset-phy-on-wake;
622 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
626 clocks = <&cru HCLK_OTG0>;
627 clock-names = "otg";
629 g-np-tx-fifo-size = <16>;
630 g-rx-fifo-size = <275>;
631 g-tx-fifo-size = <256 128 128 64 64 32>;
633 phy-names = "usb2-phy";
638 compatible = "generic-ehci";
641 clocks = <&cru HCLK_HSIC>;
645 dmac_bus_ns: dma-controller@ff600000 {
650 #dma-cells = <1>;
651 arm,pl330-broken-no-flushp;
652 arm,pl330-periph-burst;
653 clocks = <&cru ACLK_DMAC1>;
654 clock-names = "apb_pclk";
659 compatible = "rockchip,rk3288-i2c";
662 #address-cells = <1>;
663 #size-cells = <0>;
664 clock-names = "i2c";
665 clocks = <&cru PCLK_I2C0>;
666 pinctrl-names = "default";
667 pinctrl-0 = <&i2c0_xfer>;
672 compatible = "rockchip,rk3288-i2c";
675 #address-cells = <1>;
676 #size-cells = <0>;
677 clock-names = "i2c";
678 clocks = <&cru PCLK_I2C2>;
679 pinctrl-names = "default";
680 pinctrl-0 = <&i2c2_xfer>;
685 compatible = "rockchip,rk3288-pwm";
687 #pwm-cells = <3>;
688 pinctrl-names = "default";
689 pinctrl-0 = <&pwm0_pin>;
690 clocks = <&cru PCLK_RKPWM>;
695 compatible = "rockchip,rk3288-pwm";
697 #pwm-cells = <3>;
698 pinctrl-names = "default";
699 pinctrl-0 = <&pwm1_pin>;
700 clocks = <&cru PCLK_RKPWM>;
705 compatible = "rockchip,rk3288-pwm";
707 #pwm-cells = <3>;
708 pinctrl-names = "default";
709 pinctrl-0 = <&pwm2_pin>;
710 clocks = <&cru PCLK_RKPWM>;
715 compatible = "rockchip,rk3288-pwm";
717 #pwm-cells = <3>;
718 pinctrl-names = "default";
719 pinctrl-0 = <&pwm3_pin>;
720 clocks = <&cru PCLK_RKPWM>;
725 compatible = "mmio-sram";
727 #address-cells = <1>;
728 #size-cells = <1>;
730 smp-sram@0 {
731 compatible = "rockchip,rk3066-smp-sram";
737 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
741 pmu: power-management@ff730000 {
742 compatible = "rockchip,rk3288-pmu", "syscon", "simple-mfd";
745 power: power-controller {
746 compatible = "rockchip,rk3288-power-controller";
747 #power-domain-cells = <1>;
748 #address-cells = <1>;
749 #size-cells = <0>;
751 assigned-clocks = <&cru SCLK_EDP_24M>;
752 assigned-clock-parents = <&xin24m>;
777 power-domain@RK3288_PD_VIO {
779 clocks = <&cru ACLK_IEP>,
780 <&cru ACLK_ISP>,
781 <&cru ACLK_RGA>,
782 <&cru ACLK_VIP>,
783 <&cru ACLK_VOP0>,
784 <&cru ACLK_VOP1>,
785 <&cru DCLK_VOP0>,
786 <&cru DCLK_VOP1>,
787 <&cru HCLK_IEP>,
788 <&cru HCLK_ISP>,
789 <&cru HCLK_RGA>,
790 <&cru HCLK_VIP>,
791 <&cru HCLK_VOP0>,
792 <&cru HCLK_VOP1>,
793 <&cru PCLK_EDP_CTRL>,
794 <&cru PCLK_HDMI_CTRL>,
795 <&cru PCLK_LVDS_PHY>,
796 <&cru PCLK_MIPI_CSI>,
797 <&cru PCLK_MIPI_DSI0>,
798 <&cru PCLK_MIPI_DSI1>,
799 <&cru SCLK_EDP_24M>,
800 <&cru SCLK_EDP>,
801 <&cru SCLK_ISP_JPE>,
802 <&cru SCLK_ISP>,
803 <&cru SCLK_RGA>;
813 #power-domain-cells = <0>;
820 power-domain@RK3288_PD_HEVC {
822 clocks = <&cru ACLK_HEVC>,
823 <&cru SCLK_HEVC_CABAC>,
824 <&cru SCLK_HEVC_CORE>;
827 #power-domain-cells = <0>;
835 power-domain@RK3288_PD_VIDEO {
837 clocks = <&cru ACLK_VCODEC>,
838 <&cru HCLK_VCODEC>;
840 #power-domain-cells = <0>;
847 power-domain@RK3288_PD_GPU {
849 clocks = <&cru ACLK_GPU>;
852 #power-domain-cells = <0>;
856 reboot-mode {
857 compatible = "syscon-reboot-mode";
859 mode-normal = <BOOT_NORMAL>;
860 mode-recovery = <BOOT_RECOVERY>;
861 mode-bootloader = <BOOT_FASTBOOT>;
862 mode-loader = <BOOT_BL_DOWNLOAD>;
867 compatible = "rockchip,rk3288-sgrf", "syscon";
871 cru: clock-controller@ff760000 {
872 compatible = "rockchip,rk3288-cru";
875 clock-names = "xin24m";
877 #clock-cells = <1>;
878 #reset-cells = <1>;
879 assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>,
880 <&cru PLL_NPLL>, <&cru ACLK_CPU>,
881 <&cru HCLK_CPU>, <&cru PCLK_CPU>,
882 <&cru ACLK_PERI>, <&cru HCLK_PERI>,
883 <&cru PCLK_PERI>;
884 assigned-clock-rates = <594000000>, <400000000>,
892 compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd";
895 edp_phy: edp-phy {
896 compatible = "rockchip,rk3288-dp-phy";
897 clocks = <&cru SCLK_EDP_24M>;
898 clock-names = "24m";
899 #phy-cells = <0>;
903 io_domains: io-domains {
904 compatible = "rockchip,rk3288-io-voltage-domain";
909 compatible = "rockchip,rk3288-usb-phy";
910 #address-cells = <1>;
911 #size-cells = <0>;
914 usbphy0: usb-phy@320 {
915 #phy-cells = <0>;
917 clocks = <&cru SCLK_OTGPHY0>;
918 clock-names = "phyclk";
919 #clock-cells = <0>;
920 resets = <&cru SRST_USBOTG_PHY>;
921 reset-names = "phy-reset";
924 usbphy1: usb-phy@334 {
925 #phy-cells = <0>;
927 clocks = <&cru SCLK_OTGPHY1>;
928 clock-names = "phyclk";
929 #clock-cells = <0>;
930 resets = <&cru SRST_USBHOST0_PHY>;
931 reset-names = "phy-reset";
934 usbphy2: usb-phy@348 {
935 #phy-cells = <0>;
937 clocks = <&cru SCLK_OTGPHY2>;
938 clock-names = "phyclk";
939 #clock-cells = <0>;
940 resets = <&cru SRST_USBHOST1_PHY>;
941 reset-names = "phy-reset";
947 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
949 clocks = <&cru PCLK_WDT>;
955 compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif";
957 #sound-dai-cells = <0>;
958 clocks = <&cru SCLK_SPDIF8CH>, <&cru HCLK_SPDIF8CH>;
959 clock-names = "mclk", "hclk";
961 dma-names = "tx";
963 pinctrl-names = "default";
964 pinctrl-0 = <&spdif_tx>;
970 compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
972 #sound-dai-cells = <0>;
974 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0>;
975 clock-names = "i2s_clk", "i2s_hclk";
977 dma-names = "tx", "rx";
978 pinctrl-names = "default";
979 pinctrl-0 = <&i2s0_bus>;
980 rockchip,playback-channels = <8>;
981 rockchip,capture-channels = <2>;
986 compatible = "rockchip,rk3288-crypto";
989 clocks = <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>,
990 <&cru SCLK_CRYPTO>, <&cru ACLK_DMAC1>;
991 clock-names = "aclk", "hclk", "sclk", "apb_pclk";
992 resets = <&cru SRST_CRYPTO>;
993 reset-names = "crypto-rst";
1000 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
1001 clock-names = "aclk", "iface";
1002 #iommu-cells = <0>;
1010 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>;
1011 clock-names = "aclk", "iface";
1012 #iommu-cells = <0>;
1013 rockchip,disable-mmu-reset;
1018 compatible = "rockchip,rk3288-rga";
1021 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
1022 clock-names = "aclk", "hclk", "sclk";
1023 power-domains = <&power RK3288_PD_VIO>;
1024 resets = <&cru SRST_RGA_CORE>, <&cru SRST_RGA_AXI>, <&cru SRST_RGA_AHB>;
1025 reset-names = "core", "axi", "ahb";
1029 compatible = "rockchip,rk3288-vop";
1032 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1033 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1034 power-domains = <&power RK3288_PD_VIO>;
1035 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
1036 reset-names = "axi", "ahb", "dclk";
1041 #address-cells = <1>;
1042 #size-cells = <0>;
1046 remote-endpoint = <&hdmi_in_vopb>;
1051 remote-endpoint = <&edp_in_vopb>;
1056 remote-endpoint = <&mipi_in_vopb>;
1061 remote-endpoint = <&lvds_in_vopb>;
1070 clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
1071 clock-names = "aclk", "iface";
1072 power-domains = <&power RK3288_PD_VIO>;
1073 #iommu-cells = <0>;
1078 compatible = "rockchip,rk3288-vop";
1081 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1082 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1083 power-domains = <&power RK3288_PD_VIO>;
1084 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
1085 reset-names = "axi", "ahb", "dclk";
1090 #address-cells = <1>;
1091 #size-cells = <0>;
1095 remote-endpoint = <&hdmi_in_vopl>;
1100 remote-endpoint = <&edp_in_vopl>;
1105 remote-endpoint = <&mipi_in_vopl>;
1110 remote-endpoint = <&lvds_in_vopl>;
1119 clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
1120 clock-names = "aclk", "iface";
1121 power-domains = <&power RK3288_PD_VIO>;
1122 #iommu-cells = <0>;
1127 compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
1130 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_DSI0>;
1131 clock-names = "ref", "pclk";
1132 power-domains = <&power RK3288_PD_VIO>;
1137 #address-cells = <1>;
1138 #size-cells = <0>;
1142 #address-cells = <1>;
1143 #size-cells = <0>;
1147 remote-endpoint = <&vopb_out_mipi>;
1152 remote-endpoint = <&vopl_out_mipi>;
1163 compatible = "rockchip,rk3288-lvds";
1165 clocks = <&cru PCLK_LVDS_PHY>;
1166 clock-names = "pclk_lvds";
1167 pinctrl-names = "lcdc";
1168 pinctrl-0 = <&lcdc_ctl>;
1169 power-domains = <&power RK3288_PD_VIO>;
1174 #address-cells = <1>;
1175 #size-cells = <0>;
1179 #address-cells = <1>;
1180 #size-cells = <0>;
1184 remote-endpoint = <&vopb_out_lvds>;
1189 remote-endpoint = <&vopl_out_lvds>;
1200 compatible = "rockchip,rk3288-dp";
1203 clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1204 clock-names = "dp", "pclk";
1206 phy-names = "dp";
1207 power-domains = <&power RK3288_PD_VIO>;
1208 resets = <&cru SRST_EDP>;
1209 reset-names = "dp";
1214 #address-cells = <1>;
1215 #size-cells = <0>;
1219 #address-cells = <1>;
1220 #size-cells = <0>;
1224 remote-endpoint = <&vopb_out_edp>;
1229 remote-endpoint = <&vopl_out_edp>;
1240 compatible = "rockchip,rk3288-dw-hdmi";
1242 reg-io-width = <4>;
1243 #sound-dai-cells = <0>;
1246 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>, <&cru SCLK_HDMI_CEC>;
1247 clock-names = "iahb", "isfr", "cec";
1248 power-domains = <&power RK3288_PD_VIO>;
1253 #address-cells = <1>;
1254 #size-cells = <0>;
1257 remote-endpoint = <&vopb_out_hdmi>;
1261 remote-endpoint = <&vopl_out_hdmi>;
1267 vpu: video-codec@ff9a0000 {
1268 compatible = "rockchip,rk3288-vpu";
1272 interrupt-names = "vepu", "vdpu";
1273 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1274 clock-names = "aclk", "hclk";
1276 power-domains = <&power RK3288_PD_VIDEO>;
1283 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1284 clock-names = "aclk", "iface";
1285 #iommu-cells = <0>;
1286 power-domains = <&power RK3288_PD_VIDEO>;
1293 clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>;
1294 clock-names = "aclk", "iface";
1295 #iommu-cells = <0>;
1300 compatible = "rockchip,rk3288-mali", "arm,mali-t760";
1305 interrupt-names = "job", "mmu", "gpu";
1306 clocks = <&cru ACLK_GPU>;
1307 operating-points-v2 = <&gpu_opp_table>;
1308 #cooling-cells = <2>; /* min followed by max */
1309 power-domains = <&power RK3288_PD_GPU>;
1313 gpu_opp_table: opp-table-1 {
1314 compatible = "operating-points-v2";
1316 opp-100000000 {
1317 opp-hz = /bits/ 64 <100000000>;
1318 opp-microvolt = <950000>;
1320 opp-200000000 {
1321 opp-hz = /bits/ 64 <200000000>;
1322 opp-microvolt = <950000>;
1324 opp-300000000 {
1325 opp-hz = /bits/ 64 <300000000>;
1326 opp-microvolt = <1000000>;
1328 opp-400000000 {
1329 opp-hz = /bits/ 64 <400000000>;
1330 opp-microvolt = <1100000>;
1332 opp-600000000 {
1333 opp-hz = /bits/ 64 <600000000>;
1334 opp-microvolt = <1250000>;
1339 compatible = "rockchip,rk3288-qos", "syscon";
1344 compatible = "rockchip,rk3288-qos", "syscon";
1349 compatible = "rockchip,rk3288-qos", "syscon";
1354 compatible = "rockchip,rk3288-qos", "syscon";
1359 compatible = "rockchip,rk3288-qos", "syscon";
1364 compatible = "rockchip,rk3288-qos", "syscon";
1369 compatible = "rockchip,rk3288-qos", "syscon";
1374 compatible = "rockchip,rk3288-qos", "syscon";
1379 compatible = "rockchip,rk3288-qos", "syscon";
1384 compatible = "rockchip,rk3288-qos", "syscon";
1389 compatible = "rockchip,rk3288-qos", "syscon";
1394 compatible = "rockchip,rk3288-qos", "syscon";
1399 compatible = "rockchip,rk3288-qos", "syscon";
1404 compatible = "rockchip,rk3288-qos", "syscon";
1408 dmac_bus_s: dma-controller@ffb20000 {
1413 #dma-cells = <1>;
1414 arm,pl330-broken-no-flushp;
1415 arm,pl330-periph-burst;
1416 clocks = <&cru ACLK_DMAC1>;
1417 clock-names = "apb_pclk";
1421 compatible = "rockchip,rk3288-efuse";
1423 #address-cells = <1>;
1424 #size-cells = <1>;
1425 clocks = <&cru PCLK_EFUSE256>;
1426 clock-names = "pclk_efuse";
1428 cpu_id: cpu-id@7 {
1436 gic: interrupt-controller@ffc01000 {
1437 compatible = "arm,gic-400";
1438 interrupt-controller;
1439 #interrupt-cells = <3>;
1440 #address-cells = <0>;
1450 compatible = "rockchip,rk3288-pinctrl";
1453 #address-cells = <2>;
1454 #size-cells = <2>;
1458 compatible = "rockchip,gpio-bank";
1461 clocks = <&cru PCLK_GPIO0>;
1463 gpio-controller;
1464 #gpio-cells = <2>;
1466 interrupt-controller;
1467 #interrupt-cells = <2>;
1471 compatible = "rockchip,gpio-bank";
1474 clocks = <&cru PCLK_GPIO1>;
1476 gpio-controller;
1477 #gpio-cells = <2>;
1479 interrupt-controller;
1480 #interrupt-cells = <2>;
1484 compatible = "rockchip,gpio-bank";
1487 clocks = <&cru PCLK_GPIO2>;
1489 gpio-controller;
1490 #gpio-cells = <2>;
1492 interrupt-controller;
1493 #interrupt-cells = <2>;
1497 compatible = "rockchip,gpio-bank";
1500 clocks = <&cru PCLK_GPIO3>;
1502 gpio-controller;
1503 #gpio-cells = <2>;
1505 interrupt-controller;
1506 #interrupt-cells = <2>;
1510 compatible = "rockchip,gpio-bank";
1513 clocks = <&cru PCLK_GPIO4>;
1515 gpio-controller;
1516 #gpio-cells = <2>;
1518 interrupt-controller;
1519 #interrupt-cells = <2>;
1523 compatible = "rockchip,gpio-bank";
1526 clocks = <&cru PCLK_GPIO5>;
1528 gpio-controller;
1529 #gpio-cells = <2>;
1531 interrupt-controller;
1532 #interrupt-cells = <2>;
1536 compatible = "rockchip,gpio-bank";
1539 clocks = <&cru PCLK_GPIO6>;
1541 gpio-controller;
1542 #gpio-cells = <2>;
1544 interrupt-controller;
1545 #interrupt-cells = <2>;
1549 compatible = "rockchip,gpio-bank";
1552 clocks = <&cru PCLK_GPIO7>;
1554 gpio-controller;
1555 #gpio-cells = <2>;
1557 interrupt-controller;
1558 #interrupt-cells = <2>;
1562 compatible = "rockchip,gpio-bank";
1565 clocks = <&cru PCLK_GPIO8>;
1567 gpio-controller;
1568 #gpio-cells = <2>;
1570 interrupt-controller;
1571 #interrupt-cells = <2>;
1575 hdmi_cec_c0: hdmi-cec-c0 {
1579 hdmi_cec_c7: hdmi-cec-c7 {
1583 hdmi_ddc: hdmi-ddc {
1588 hdmi_ddc_unwedge: hdmi-ddc-unwedge {
1594 pcfg_output_low: pcfg-output-low {
1595 output-low;
1598 pcfg_pull_up: pcfg-pull-up {
1599 bias-pull-up;
1602 pcfg_pull_down: pcfg-pull-down {
1603 bias-pull-down;
1606 pcfg_pull_none: pcfg-pull-none {
1607 bias-disable;
1610 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1611 bias-disable;
1612 drive-strength = <12>;
1616 global_pwroff: global-pwroff {
1620 ddrio_pwroff: ddrio-pwroff {
1624 ddr0_retention: ddr0-retention {
1628 ddr1_retention: ddr1-retention {
1634 edp_hpd: edp-hpd {
1640 i2c0_xfer: i2c0-xfer {
1647 i2c1_xfer: i2c1-xfer {
1654 i2c2_xfer: i2c2-xfer {
1661 i2c3_xfer: i2c3-xfer {
1668 i2c4_xfer: i2c4-xfer {
1675 i2c5_xfer: i2c5-xfer {
1682 i2s0_bus: i2s0-bus {
1693 lcdc_ctl: lcdc-ctl {
1702 sdmmc_clk: sdmmc-clk {
1706 sdmmc_cmd: sdmmc-cmd {
1710 sdmmc_cd: sdmmc-cd {
1714 sdmmc_bus1: sdmmc-bus1 {
1718 sdmmc_bus4: sdmmc-bus4 {
1727 sdio0_bus1: sdio0-bus1 {
1731 sdio0_bus4: sdio0-bus4 {
1738 sdio0_cmd: sdio0-cmd {
1742 sdio0_clk: sdio0-clk {
1746 sdio0_cd: sdio0-cd {
1750 sdio0_wp: sdio0-wp {
1754 sdio0_pwr: sdio0-pwr {
1758 sdio0_bkpwr: sdio0-bkpwr {
1762 sdio0_int: sdio0-int {
1768 sdio1_bus1: sdio1-bus1 {
1772 sdio1_bus4: sdio1-bus4 {
1779 sdio1_cd: sdio1-cd {
1783 sdio1_wp: sdio1-wp {
1787 sdio1_bkpwr: sdio1-bkpwr {
1791 sdio1_int: sdio1-int {
1795 sdio1_cmd: sdio1-cmd {
1799 sdio1_clk: sdio1-clk {
1803 sdio1_pwr: sdio1-pwr {
1809 emmc_clk: emmc-clk {
1813 emmc_cmd: emmc-cmd {
1817 emmc_pwr: emmc-pwr {
1821 emmc_bus1: emmc-bus1 {
1825 emmc_bus4: emmc-bus4 {
1832 emmc_bus8: emmc-bus8 {
1845 spi0_clk: spi0-clk {
1848 spi0_cs0: spi0-cs0 {
1851 spi0_tx: spi0-tx {
1854 spi0_rx: spi0-rx {
1857 spi0_cs1: spi0-cs1 {
1862 spi1_clk: spi1-clk {
1865 spi1_cs0: spi1-cs0 {
1868 spi1_rx: spi1-rx {
1871 spi1_tx: spi1-tx {
1877 spi2_cs1: spi2-cs1 {
1880 spi2_clk: spi2-clk {
1883 spi2_cs0: spi2-cs0 {
1886 spi2_rx: spi2-rx {
1889 spi2_tx: spi2-tx {
1895 uart0_xfer: uart0-xfer {
1900 uart0_cts: uart0-cts {
1904 uart0_rts: uart0-rts {
1910 uart1_xfer: uart1-xfer {
1915 uart1_cts: uart1-cts {
1919 uart1_rts: uart1-rts {
1925 uart2_xfer: uart2-xfer {
1933 uart3_xfer: uart3-xfer {
1938 uart3_cts: uart3-cts {
1942 uart3_rts: uart3-rts {
1948 uart4_xfer: uart4-xfer {
1953 uart4_cts: uart4-cts {
1957 uart4_rts: uart4-rts {
1963 otp_pin: otp-pin {
1967 otp_out: otp-out {
1973 pwm0_pin: pwm0-pin {
1979 pwm1_pin: pwm1-pin {
1985 pwm2_pin: pwm2-pin {
1991 pwm3_pin: pwm3-pin {
1997 rgmii_pins: rgmii-pins {
2015 rmii_pins: rmii-pins {
2030 spdif_tx: spdif-tx {