Lines Matching +full:opp +full:- +full:816000000
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include <dt-bindings/clock/rk3228-cru.h>
8 #include <dt-bindings/thermal/thermal.h>
9 #include <dt-bindings/power/rk3228-power.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
15 interrupt-parent = <&gic>;
29 #address-cells = <1>;
30 #size-cells = <0>;
34 compatible = "arm,cortex-a7";
37 operating-points-v2 = <&cpu0_opp_table>;
38 #cooling-cells = <2>; /* min followed by max */
39 clock-latency = <40000>;
41 enable-method = "psci";
46 compatible = "arm,cortex-a7";
49 operating-points-v2 = <&cpu0_opp_table>;
50 #cooling-cells = <2>; /* min followed by max */
51 enable-method = "psci";
56 compatible = "arm,cortex-a7";
59 operating-points-v2 = <&cpu0_opp_table>;
60 #cooling-cells = <2>; /* min followed by max */
61 enable-method = "psci";
66 compatible = "arm,cortex-a7";
69 operating-points-v2 = <&cpu0_opp_table>;
70 #cooling-cells = <2>; /* min followed by max */
71 enable-method = "psci";
75 cpu0_opp_table: opp-table-0 {
76 compatible = "operating-points-v2";
77 opp-shared;
79 opp-408000000 {
80 opp-hz = /bits/ 64 <408000000>;
81 opp-microvolt = <950000>;
82 clock-latency-ns = <40000>;
83 opp-suspend;
85 opp-600000000 {
86 opp-hz = /bits/ 64 <600000000>;
87 opp-microvolt = <975000>;
89 opp-816000000 {
90 opp-hz = /bits/ 64 <816000000>;
91 opp-microvolt = <1000000>;
93 opp-1008000000 {
94 opp-hz = /bits/ 64 <1008000000>;
95 opp-microvolt = <1175000>;
97 opp-1200000000 {
98 opp-hz = /bits/ 64 <1200000000>;
99 opp-microvolt = <1275000>;
103 arm-pmu {
104 compatible = "arm,cortex-a7-pmu";
109 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
113 compatible = "arm,psci-1.0", "arm,psci-0.2";
118 compatible = "arm,armv7-timer";
119 arm,cpu-registers-not-fw-configured;
124 clock-frequency = <24000000>;
128 compatible = "fixed-clock";
129 clock-frequency = <24000000>;
130 clock-output-names = "xin24m";
131 #clock-cells = <0>;
134 display_subsystem: display-subsystem {
135 compatible = "rockchip,display-subsystem";
140 compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
143 clock-names = "i2s_clk", "i2s_hclk";
146 dma-names = "tx", "rx";
147 pinctrl-names = "default";
148 pinctrl-0 = <&i2s1_bus>;
153 compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
156 clock-names = "i2s_clk", "i2s_hclk";
159 dma-names = "tx", "rx";
164 compatible = "rockchip,rk3228-spdif";
168 clock-names = "mclk", "hclk";
170 dma-names = "tx";
171 pinctrl-names = "default";
172 pinctrl-0 = <&spdif_tx>;
177 compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
180 clock-names = "i2s_clk", "i2s_hclk";
183 dma-names = "tx", "rx";
188 compatible = "rockchip,rk3228-grf", "syscon", "simple-mfd";
190 #address-cells = <1>;
191 #size-cells = <1>;
193 io_domains: io-domains {
194 compatible = "rockchip,rk3228-io-voltage-domain";
198 power: power-controller {
199 compatible = "rockchip,rk3228-power-controller";
200 #power-domain-cells = <1>;
201 #address-cells = <1>;
202 #size-cells = <0>;
204 power-domain@RK3228_PD_VIO {
217 #power-domain-cells = <0>;
220 power-domain@RK3228_PD_VOP {
226 #power-domain-cells = <0>;
229 power-domain@RK3228_PD_VPU {
234 #power-domain-cells = <0>;
237 power-domain@RK3228_PD_RKVDEC {
245 #power-domain-cells = <0>;
248 power-domain@RK3228_PD_GPU {
252 #power-domain-cells = <0>;
257 compatible = "rockchip,rk3228-usb2phy";
260 clock-names = "phyclk";
261 clock-output-names = "usb480m_phy0";
262 #clock-cells = <0>;
265 u2phy0_otg: otg-port {
269 interrupt-names = "otg-bvalid", "otg-id",
271 #phy-cells = <0>;
275 u2phy0_host: host-port {
277 interrupt-names = "linestate";
278 #phy-cells = <0>;
284 compatible = "rockchip,rk3228-usb2phy";
287 clock-names = "phyclk";
288 clock-output-names = "usb480m_phy1";
289 #clock-cells = <0>;
292 u2phy1_otg: otg-port {
294 interrupt-names = "linestate";
295 #phy-cells = <0>;
299 u2phy1_host: host-port {
301 interrupt-names = "linestate";
302 #phy-cells = <0>;
309 compatible = "snps,dw-apb-uart";
312 clock-frequency = <24000000>;
314 clock-names = "baudclk", "apb_pclk";
315 pinctrl-names = "default";
316 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
317 reg-shift = <2>;
318 reg-io-width = <4>;
323 compatible = "snps,dw-apb-uart";
326 clock-frequency = <24000000>;
328 clock-names = "baudclk", "apb_pclk";
329 pinctrl-names = "default";
330 pinctrl-0 = <&uart1_xfer>;
331 reg-shift = <2>;
332 reg-io-width = <4>;
337 compatible = "snps,dw-apb-uart";
340 clock-frequency = <24000000>;
342 clock-names = "baudclk", "apb_pclk";
343 pinctrl-names = "default";
344 pinctrl-0 = <&uart2_xfer>;
345 reg-shift = <2>;
346 reg-io-width = <4>;
351 compatible = "rockchip,rk3228-efuse";
354 clock-names = "pclk_efuse";
355 #address-cells = <1>;
356 #size-cells = <1>;
368 compatible = "rockchip,rk3228-i2c";
371 #address-cells = <1>;
372 #size-cells = <0>;
373 clock-names = "i2c";
375 pinctrl-names = "default";
376 pinctrl-0 = <&i2c0_xfer>;
381 compatible = "rockchip,rk3228-i2c";
384 #address-cells = <1>;
385 #size-cells = <0>;
386 clock-names = "i2c";
388 pinctrl-names = "default";
389 pinctrl-0 = <&i2c1_xfer>;
394 compatible = "rockchip,rk3228-i2c";
397 #address-cells = <1>;
398 #size-cells = <0>;
399 clock-names = "i2c";
401 pinctrl-names = "default";
402 pinctrl-0 = <&i2c2_xfer>;
407 compatible = "rockchip,rk3228-i2c";
410 #address-cells = <1>;
411 #size-cells = <0>;
412 clock-names = "i2c";
414 pinctrl-names = "default";
415 pinctrl-0 = <&i2c3_xfer>;
420 compatible = "rockchip,rk3228-spi";
423 #address-cells = <1>;
424 #size-cells = <0>;
426 clock-names = "spiclk", "apb_pclk";
427 pinctrl-names = "default";
428 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0 &spi0_cs1>;
433 compatible = "rockchip,rk3228-wdt", "snps,dw-wdt";
441 compatible = "rockchip,rk3288-pwm";
443 #pwm-cells = <3>;
445 pinctrl-names = "default";
446 pinctrl-0 = <&pwm0_pin>;
451 compatible = "rockchip,rk3288-pwm";
453 #pwm-cells = <3>;
455 pinctrl-names = "default";
456 pinctrl-0 = <&pwm1_pin>;
461 compatible = "rockchip,rk3288-pwm";
463 #pwm-cells = <3>;
465 pinctrl-names = "default";
466 pinctrl-0 = <&pwm2_pin>;
471 compatible = "rockchip,rk3288-pwm";
473 #pwm-cells = <2>;
475 pinctrl-names = "default";
476 pinctrl-0 = <&pwm3_pin>;
481 compatible = "rockchip,rk3228-timer", "rockchip,rk3288-timer";
485 clock-names = "pclk", "timer";
488 cru: clock-controller@110e0000 {
489 compatible = "rockchip,rk3228-cru";
492 clock-names = "xin24m";
494 #clock-cells = <1>;
495 #reset-cells = <1>;
496 assigned-clocks =
502 assigned-clock-rates =
503 <594000000>, <816000000>,
510 pdma: dma-controller@110f0000 {
515 #dma-cells = <1>;
516 arm,pl330-periph-burst;
518 clock-names = "apb_pclk";
521 thermal-zones {
522 cpu_thermal: cpu-thermal {
523 polling-delay-passive = <100>; /* milliseconds */
524 polling-delay = <5000>; /* milliseconds */
526 thermal-sensors = <&tsadc 0>;
546 cooling-maps {
549 cooling-device =
557 cooling-device =
568 compatible = "rockchip,rk3228-tsadc";
572 clock-names = "tsadc", "apb_pclk";
573 assigned-clocks = <&cru SCLK_TSADC>;
574 assigned-clock-rates = <32768>;
576 reset-names = "tsadc-apb";
577 pinctrl-names = "init", "default", "sleep";
578 pinctrl-0 = <&otp_pin>;
579 pinctrl-1 = <&otp_out>;
580 pinctrl-2 = <&otp_pin>;
581 #thermal-sensor-cells = <1>;
582 rockchip,hw-tshut-temp = <95000>;
586 hdmi_phy: hdmi-phy@12030000 {
587 compatible = "rockchip,rk3228-hdmi-phy";
590 clock-names = "sysclk", "refoclk", "refpclk";
591 #clock-cells = <0>;
592 clock-output-names = "hdmiphy_phy";
593 #phy-cells = <0>;
598 compatible = "rockchip,rk3228-mali", "arm,mali-400";
606 interrupt-names = "gp",
613 clock-names = "bus", "core";
614 power-domains = <&power RK3228_PD_GPU>;
619 vpu: video-codec@20020000 {
620 compatible = "rockchip,rk3228-vpu", "rockchip,rk3399-vpu";
624 interrupt-names = "vepu", "vdpu";
626 clock-names = "aclk", "hclk";
628 power-domains = <&power RK3228_PD_VPU>;
636 clock-names = "aclk", "iface";
637 power-domains = <&power RK3228_PD_VPU>;
638 #iommu-cells = <0>;
641 vdec: video-codec@20030000 {
642 compatible = "rockchip,rk3228-vdec", "rockchip,rk3399-vdec";
647 clock-names = "axi", "ahb", "cabac", "core";
648 assigned-clocks = <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>;
649 assigned-clock-rates = <300000000>, <300000000>;
651 power-domains = <&power RK3228_PD_RKVDEC>;
659 clock-names = "aclk", "iface";
660 power-domains = <&power RK3228_PD_RKVDEC>;
661 #iommu-cells = <0>;
665 compatible = "rockchip,rk3228-vop";
669 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
671 reset-names = "axi", "ahb", "dclk";
673 power-domains = <&power RK3228_PD_VOP>;
677 #address-cells = <1>;
678 #size-cells = <0>;
682 remote-endpoint = <&hdmi_in_vop>;
692 clock-names = "aclk", "iface";
693 power-domains = <&power RK3228_PD_VOP>;
694 #iommu-cells = <0>;
699 compatible = "rockchip,rk3228-rga", "rockchip,rk3288-rga";
703 clock-names = "aclk", "hclk", "sclk";
704 power-domains = <&power RK3228_PD_VIO>;
706 reset-names = "core", "axi", "ahb";
714 clock-names = "aclk", "iface";
715 power-domains = <&power RK3228_PD_VIO>;
716 #iommu-cells = <0>;
721 compatible = "rockchip,rk3228-dw-hdmi";
723 reg-io-width = <4>;
725 assigned-clocks = <&cru SCLK_HDMI_PHY>;
726 assigned-clock-parents = <&hdmi_phy>;
728 clock-names = "iahb", "isfr", "cec";
729 pinctrl-names = "default";
730 pinctrl-0 = <&hdmii2c_xfer &hdmi_hpd &hdmi_cec>;
732 reset-names = "hdmi";
734 phy-names = "hdmi";
740 #address-cells = <1>;
741 #size-cells = <0>;
744 remote-endpoint = <&vop_out_hdmi>;
751 compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";
756 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
757 fifo-depth = <0x100>;
758 pinctrl-names = "default";
759 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;
764 compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";
769 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
770 fifo-depth = <0x100>;
771 pinctrl-names = "default";
772 pinctrl-0 = <&sdio_clk &sdio_cmd &sdio_bus4>;
777 compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";
780 clock-frequency = <37500000>;
781 max-frequency = <37500000>;
784 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
785 bus-width = <8>;
786 rockchip,default-sample-phase = <158>;
787 fifo-depth = <0x100>;
788 pinctrl-names = "default";
789 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
791 reset-names = "reset";
796 compatible = "rockchip,rk3228-usb", "rockchip,rk3066-usb",
801 clock-names = "otg";
803 g-np-tx-fifo-size = <16>;
804 g-rx-fifo-size = <280>;
805 g-tx-fifo-size = <256 128 128 64 32 16>;
807 phy-names = "usb2-phy";
812 compatible = "generic-ehci";
817 phy-names = "usb";
822 compatible = "generic-ohci";
827 phy-names = "usb";
832 compatible = "generic-ehci";
837 phy-names = "usb";
842 compatible = "generic-ohci";
847 phy-names = "usb";
852 compatible = "generic-ehci";
857 phy-names = "usb";
862 compatible = "generic-ohci";
867 phy-names = "usb";
872 compatible = "rockchip,rk3228-gmac";
875 interrupt-names = "macirq";
880 clock-names = "stmmaceth", "mac_clk_rx",
885 reset-names = "stmmaceth";
891 compatible = "rockchip,rk3228-qos", "syscon";
896 compatible = "rockchip,rk3228-qos", "syscon";
901 compatible = "rockchip,rk3228-qos", "syscon";
906 compatible = "rockchip,rk3228-qos", "syscon";
911 compatible = "rockchip,rk3228-qos", "syscon";
916 compatible = "rockchip,rk3228-qos", "syscon";
921 compatible = "rockchip,rk3228-qos", "syscon";
926 compatible = "rockchip,rk3228-qos", "syscon";
931 compatible = "rockchip,rk3228-qos", "syscon";
935 gic: interrupt-controller@32010000 {
936 compatible = "arm,gic-400";
937 interrupt-controller;
938 #interrupt-cells = <3>;
939 #address-cells = <0>;
949 compatible = "rockchip,rk3228-pinctrl";
951 #address-cells = <1>;
952 #size-cells = <1>;
956 compatible = "rockchip,gpio-bank";
961 gpio-controller;
962 #gpio-cells = <2>;
964 interrupt-controller;
965 #interrupt-cells = <2>;
969 compatible = "rockchip,gpio-bank";
974 gpio-controller;
975 #gpio-cells = <2>;
977 interrupt-controller;
978 #interrupt-cells = <2>;
982 compatible = "rockchip,gpio-bank";
987 gpio-controller;
988 #gpio-cells = <2>;
990 interrupt-controller;
991 #interrupt-cells = <2>;
995 compatible = "rockchip,gpio-bank";
1000 gpio-controller;
1001 #gpio-cells = <2>;
1003 interrupt-controller;
1004 #interrupt-cells = <2>;
1007 pcfg_pull_up: pcfg-pull-up {
1008 bias-pull-up;
1011 pcfg_pull_down: pcfg-pull-down {
1012 bias-pull-down;
1015 pcfg_pull_none: pcfg-pull-none {
1016 bias-disable;
1019 pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma {
1020 drive-strength = <12>;
1024 sdmmc_clk: sdmmc-clk {
1028 sdmmc_cmd: sdmmc-cmd {
1032 sdmmc_bus4: sdmmc-bus4 {
1041 sdio_clk: sdio-clk {
1045 sdio_cmd: sdio-cmd {
1049 sdio_bus4: sdio-bus4 {
1058 emmc_clk: emmc-clk {
1062 emmc_cmd: emmc-cmd {
1066 emmc_bus8: emmc-bus8 {
1079 rgmii_pins: rgmii-pins {
1097 rmii_pins: rmii-pins {
1110 phy_pins: phy-pins {
1117 hdmi_hpd: hdmi-hpd {
1121 hdmii2c_xfer: hdmii2c-xfer {
1126 hdmi_cec: hdmi-cec {
1132 i2c0_xfer: i2c0-xfer {
1139 i2c1_xfer: i2c1-xfer {
1146 i2c2_xfer: i2c2-xfer {
1153 i2c3_xfer: i2c3-xfer {
1160 spi0_clk: spi0-clk {
1163 spi0_cs0: spi0-cs0 {
1166 spi0_tx: spi0-tx {
1169 spi0_rx: spi0-rx {
1172 spi0_cs1: spi0-cs1 {
1178 spi1_clk: spi1-clk {
1181 spi1_cs0: spi1-cs0 {
1184 spi1_rx: spi1-rx {
1187 spi1_tx: spi1-tx {
1190 spi1_cs1: spi1-cs1 {
1196 i2s1_bus: i2s1-bus {
1210 pwm0_pin: pwm0-pin {
1216 pwm1_pin: pwm1-pin {
1222 pwm2_pin: pwm2-pin {
1228 pwm3_pin: pwm3-pin {
1234 spdif_tx: spdif-tx {
1240 otp_pin: otp-pin {
1244 otp_out: otp-out {
1250 uart0_xfer: uart0-xfer {
1255 uart0_cts: uart0-cts {
1259 uart0_rts: uart0-rts {
1265 uart1_xfer: uart1-xfer {
1270 uart1_cts: uart1-cts {
1274 uart1_rts: uart1-rts {
1280 uart2_xfer: uart2-xfer {
1285 uart21_xfer: uart21-xfer {
1290 uart2_cts: uart2-cts {
1294 uart2_rts: uart2-rts {