Lines Matching full:cru
7 #include <dt-bindings/clock/rk3228-cru.h>
36 resets = <&cru SRST_CORE0>;
40 clocks = <&cru ARMCLK>;
48 resets = <&cru SRST_CORE1>;
58 resets = <&cru SRST_CORE2>;
68 resets = <&cru SRST_CORE3>;
144 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
157 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
167 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>;
181 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
206 clocks = <&cru ACLK_HDCP>,
207 <&cru SCLK_HDCP>,
208 <&cru ACLK_IEP>,
209 <&cru HCLK_IEP>,
210 <&cru ACLK_RGA>,
211 <&cru HCLK_RGA>,
212 <&cru SCLK_RGA>;
222 clocks = <&cru ACLK_VOP>,
223 <&cru DCLK_VOP>,
224 <&cru HCLK_VOP>;
231 clocks = <&cru ACLK_VPU>,
232 <&cru HCLK_VPU>;
239 clocks = <&cru ACLK_RKVDEC>,
240 <&cru HCLK_RKVDEC>,
241 <&cru SCLK_VDEC_CABAC>,
242 <&cru SCLK_VDEC_CORE>;
250 clocks = <&cru ACLK_GPU>;
259 clocks = <&cru SCLK_OTGPHY0>;
286 clocks = <&cru SCLK_OTGPHY1>;
313 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
327 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
341 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
353 clocks = <&cru PCLK_EFUSE_256>;
374 clocks = <&cru PCLK_I2C0>;
387 clocks = <&cru PCLK_I2C1>;
400 clocks = <&cru PCLK_I2C2>;
413 clocks = <&cru PCLK_I2C3>;
425 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
436 clocks = <&cru PCLK_CPU>;
444 clocks = <&cru PCLK_PWM>;
454 clocks = <&cru PCLK_PWM>;
464 clocks = <&cru PCLK_PWM>;
474 clocks = <&cru PCLK_PWM>;
484 clocks = <&cru PCLK_TIMER>, <&xin24m>;
488 cru: clock-controller@110e0000 {
489 compatible = "rockchip,rk3228-cru";
497 <&cru PLL_GPLL>, <&cru ARMCLK>,
498 <&cru PLL_CPLL>, <&cru ACLK_PERI>,
499 <&cru HCLK_PERI>, <&cru PCLK_PERI>,
500 <&cru ACLK_CPU>, <&cru HCLK_CPU>,
501 <&cru PCLK_CPU>;
517 clocks = <&cru ACLK_DMAC>;
571 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
573 assigned-clocks = <&cru SCLK_TSADC>;
575 resets = <&cru SRST_TSADC>;
589 clocks = <&cru PCLK_HDMI_PHY>, <&xin24m>, <&cru DCLK_HDMI_PHY>;
612 clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;
615 resets = <&cru SRST_GPU_A>;
625 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
635 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
645 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>,
646 <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>;
648 assigned-clocks = <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>;
658 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>;
668 clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>;
670 resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>;
691 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
702 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
705 resets = <&cru SRST_RGA>, <&cru SRST_RGA_A>, <&cru SRST_RGA_H>;
713 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
725 assigned-clocks = <&cru SCLK_HDMI_PHY>;
727 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>, <&cru SCLK_HDMI_CEC>;
731 resets = <&cru SRST_HDMI_P>;
754 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
755 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
767 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
768 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
782 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
783 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
790 resets = <&cru SRST_EMMC>;
800 clocks = <&cru HCLK_OTG>;
815 clocks = <&cru HCLK_HOST0>, <&u2phy0>;
825 clocks = <&cru HCLK_HOST0>, <&u2phy0>;
835 clocks = <&cru HCLK_HOST1>, <&u2phy1>;
845 clocks = <&cru HCLK_HOST1>, <&u2phy1>;
855 clocks = <&cru HCLK_HOST2>, <&u2phy1>;
865 clocks = <&cru HCLK_HOST2>, <&u2phy1>;
876 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
877 <&cru SCLK_MAC_TX>, <&cru SCLK_MAC_REF>,
878 <&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>,
879 <&cru PCLK_GMAC>;
884 resets = <&cru SRST_GMAC>;
959 clocks = <&cru PCLK_GPIO0>;
972 clocks = <&cru PCLK_GPIO1>;
985 clocks = <&cru PCLK_GPIO2>;
998 clocks = <&cru PCLK_GPIO3>;