Lines Matching +full:ns +full:- +full:cru

1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/pinctrl/rockchip.h>
9 #include <dt-bindings/clock/rk3188-cru.h>
10 #include <dt-bindings/power/rk3188-power.h>
17 #address-cells = <1>;
18 #size-cells = <0>;
19 enable-method = "rockchip,rk3066-smp";
23 compatible = "arm,cortex-a9";
24 next-level-cache = <&L2>;
26 clock-latency = <40000>;
27 clocks = <&cru ARMCLK>;
28 operating-points-v2 = <&cpu0_opp_table>;
29 resets = <&cru SRST_CORE0>;
33 compatible = "arm,cortex-a9";
34 next-level-cache = <&L2>;
36 operating-points-v2 = <&cpu0_opp_table>;
37 resets = <&cru SRST_CORE1>;
41 compatible = "arm,cortex-a9";
42 next-level-cache = <&L2>;
44 operating-points-v2 = <&cpu0_opp_table>;
45 resets = <&cru SRST_CORE2>;
49 compatible = "arm,cortex-a9";
50 next-level-cache = <&L2>;
52 operating-points-v2 = <&cpu0_opp_table>;
53 resets = <&cru SRST_CORE3>;
57 cpu0_opp_table: opp-table-0 {
58 compatible = "operating-points-v2";
59 opp-shared;
61 opp-312000000 {
62 opp-hz = /bits/ 64 <312000000>;
63 opp-microvolt = <875000>;
64 clock-latency-ns = <40000>;
66 opp-504000000 {
67 opp-hz = /bits/ 64 <504000000>;
68 opp-microvolt = <925000>;
70 opp-600000000 {
71 opp-hz = /bits/ 64 <600000000>;
72 opp-microvolt = <950000>;
73 opp-suspend;
75 opp-816000000 {
76 opp-hz = /bits/ 64 <816000000>;
77 opp-microvolt = <975000>;
79 opp-1008000000 {
80 opp-hz = /bits/ 64 <1008000000>;
81 opp-microvolt = <1075000>;
83 opp-1200000000 {
84 opp-hz = /bits/ 64 <1200000000>;
85 opp-microvolt = <1150000>;
87 opp-1416000000 {
88 opp-hz = /bits/ 64 <1416000000>;
89 opp-microvolt = <1250000>;
91 opp-1608000000 {
92 opp-hz = /bits/ 64 <1608000000>;
93 opp-microvolt = <1350000>;
97 display-subsystem {
98 compatible = "rockchip,display-subsystem";
103 compatible = "mmio-sram";
105 #address-cells = <1>;
106 #size-cells = <1>;
109 smp-sram@0 {
110 compatible = "rockchip,rk3066-smp-sram";
116 compatible = "rockchip,rk3188-vop";
119 clocks = <&cru ACLK_LCDC0>, <&cru DCLK_LCDC0>, <&cru HCLK_LCDC0>;
120 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
121 power-domains = <&power RK3188_PD_VIO>;
122 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
123 reset-names = "axi", "ahb", "dclk";
127 #address-cells = <1>;
128 #size-cells = <0>;
133 compatible = "rockchip,rk3188-vop";
136 clocks = <&cru ACLK_LCDC1>, <&cru DCLK_LCDC1>, <&cru HCLK_LCDC1>;
137 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
138 power-domains = <&power RK3188_PD_VIO>;
139 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
140 reset-names = "axi", "ahb", "dclk";
144 #address-cells = <1>;
145 #size-cells = <0>;
150 compatible = "rockchip,rk3188-timer", "rockchip,rk3288-timer";
153 clocks = <&cru PCLK_TIMER3>, <&cru SCLK_TIMER3>;
154 clock-names = "pclk", "timer";
158 compatible = "rockchip,rk3188-timer", "rockchip,rk3288-timer";
161 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER6>;
162 clock-names = "pclk", "timer";
166 compatible = "rockchip,rk3188-i2s", "rockchip,rk3066-i2s";
169 pinctrl-names = "default";
170 pinctrl-0 = <&i2s0_bus>;
171 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0>;
172 clock-names = "i2s_clk", "i2s_hclk";
174 dma-names = "tx", "rx";
175 rockchip,playback-channels = <2>;
176 rockchip,capture-channels = <2>;
177 #sound-dai-cells = <0>;
182 compatible = "rockchip,rk3188-spdif", "rockchip,rk3066-spdif";
184 #sound-dai-cells = <0>;
185 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF>;
186 clock-names = "mclk", "hclk";
188 dma-names = "tx";
190 pinctrl-names = "default";
191 pinctrl-0 = <&spdif_tx>;
195 cru: clock-controller@20000000 { label
196 compatible = "rockchip,rk3188-cru";
199 clock-names = "xin24m";
201 #clock-cells = <1>;
202 #reset-cells = <1>;
206 compatible = "rockchip,rk3188-efuse";
208 #address-cells = <1>;
209 #size-cells = <1>;
210 clocks = <&cru PCLK_EFUSE>;
211 clock-names = "pclk_efuse";
219 compatible = "rockchip,rk3188-pinctrl";
223 #address-cells = <1>;
224 #size-cells = <1>;
228 compatible = "rockchip,rk3188-gpio-bank0";
231 clocks = <&cru PCLK_GPIO0>;
233 gpio-controller;
234 #gpio-cells = <2>;
236 interrupt-controller;
237 #interrupt-cells = <2>;
241 compatible = "rockchip,gpio-bank";
244 clocks = <&cru PCLK_GPIO1>;
246 gpio-controller;
247 #gpio-cells = <2>;
249 interrupt-controller;
250 #interrupt-cells = <2>;
254 compatible = "rockchip,gpio-bank";
257 clocks = <&cru PCLK_GPIO2>;
259 gpio-controller;
260 #gpio-cells = <2>;
262 interrupt-controller;
263 #interrupt-cells = <2>;
267 compatible = "rockchip,gpio-bank";
270 clocks = <&cru PCLK_GPIO3>;
272 gpio-controller;
273 #gpio-cells = <2>;
275 interrupt-controller;
276 #interrupt-cells = <2>;
279 pcfg_pull_up: pcfg-pull-up {
280 bias-pull-up;
283 pcfg_pull_down: pcfg-pull-down {
284 bias-pull-down;
287 pcfg_pull_none: pcfg-pull-none {
288 bias-disable;
292 emmc_clk: emmc-clk {
296 emmc_cmd: emmc-cmd {
300 emmc_rst: emmc-rst {
308 * flash/emmc is the boot-device.
313 emac_xfer: emac-xfer {
324 emac_mdio: emac-mdio {
331 i2c0_xfer: i2c0-xfer {
338 i2c1_xfer: i2c1-xfer {
345 i2c2_xfer: i2c2-xfer {
352 i2c3_xfer: i2c3-xfer {
359 i2c4_xfer: i2c4-xfer {
366 lcdc1_dclk: lcdc1-dclk {
370 lcdc1_den: lcdc1-den {
374 lcdc1_hsync: lcdc1-hsync {
378 lcdc1_vsync: lcdc1-vsync {
382 lcdc1_rgb24: lcdc1-rgb24 {
411 pwm0_out: pwm0-out {
417 pwm1_out: pwm1-out {
423 pwm2_out: pwm2-out {
429 pwm3_out: pwm3-out {
435 spi0_clk: spi0-clk {
438 spi0_cs0: spi0-cs0 {
441 spi0_tx: spi0-tx {
444 spi0_rx: spi0-rx {
447 spi0_cs1: spi0-cs1 {
453 spi1_clk: spi1-clk {
456 spi1_cs0: spi1-cs0 {
459 spi1_rx: spi1-rx {
462 spi1_tx: spi1-tx {
465 spi1_cs1: spi1-cs1 {
471 uart0_xfer: uart0-xfer {
476 uart0_cts: uart0-cts {
480 uart0_rts: uart0-rts {
486 uart1_xfer: uart1-xfer {
491 uart1_cts: uart1-cts {
495 uart1_rts: uart1-rts {
501 uart2_xfer: uart2-xfer {
509 uart3_xfer: uart3-xfer {
514 uart3_cts: uart3-cts {
518 uart3_rts: uart3-rts {
524 sd0_clk: sd0-clk {
528 sd0_cmd: sd0-cmd {
532 sd0_cd: sd0-cd {
536 sd0_wp: sd0-wp {
540 sd0_pwr: sd0-pwr {
544 sd0_bus1: sd0-bus-width1 {
548 sd0_bus4: sd0-bus-width4 {
557 sd1_clk: sd1-clk {
561 sd1_cmd: sd1-cmd {
565 sd1_cd: sd1-cd {
569 sd1_wp: sd1-wp {
573 sd1_bus1: sd1-bus-width1 {
577 sd1_bus4: sd1-bus-width4 {
586 i2s0_bus: i2s0-bus {
597 spdif_tx: spdif-tx {
605 compatible = "rockchip,rk3188-emac";
617 compatible = "rockchip,rk3188-mali", "arm,mali-400";
628 interrupt-names = "gp",
638 power-domains = <&power RK3188_PD_GPU>;
642 compatible = "rockchip,rk3188-grf", "syscon", "simple-mfd";
644 io_domains: io-domains {
645 compatible = "rockchip,rk3188-io-voltage-domain";
650 compatible = "rockchip,rk3188-usb-phy";
651 #address-cells = <1>;
652 #size-cells = <0>;
655 usbphy0: usb-phy@10c {
657 clocks = <&cru SCLK_OTGPHY0>;
658 clock-names = "phyclk";
659 #clock-cells = <0>;
660 #phy-cells = <0>;
663 usbphy1: usb-phy@11c {
665 clocks = <&cru SCLK_OTGPHY1>;
666 clock-names = "phyclk";
667 #clock-cells = <0>;
668 #phy-cells = <0>;
674 compatible = "rockchip,rk3188-i2c";
675 pinctrl-names = "default";
676 pinctrl-0 = <&i2c0_xfer>;
680 compatible = "rockchip,rk3188-i2c";
681 pinctrl-names = "default";
682 pinctrl-0 = <&i2c1_xfer>;
686 compatible = "rockchip,rk3188-i2c";
687 pinctrl-names = "default";
688 pinctrl-0 = <&i2c2_xfer>;
692 compatible = "rockchip,rk3188-i2c";
693 pinctrl-names = "default";
694 pinctrl-0 = <&i2c3_xfer>;
698 compatible = "rockchip,rk3188-i2c";
699 pinctrl-names = "default";
700 pinctrl-0 = <&i2c4_xfer>;
704 power: power-controller {
705 compatible = "rockchip,rk3188-power-controller";
706 #power-domain-cells = <1>;
707 #address-cells = <1>;
708 #size-cells = <0>;
710 power-domain@RK3188_PD_VIO {
712 clocks = <&cru ACLK_LCDC0>,
713 <&cru ACLK_LCDC1>,
714 <&cru DCLK_LCDC0>,
715 <&cru DCLK_LCDC1>,
716 <&cru HCLK_LCDC0>,
717 <&cru HCLK_LCDC1>,
718 <&cru SCLK_CIF0>,
719 <&cru ACLK_CIF0>,
720 <&cru HCLK_CIF0>,
721 <&cru ACLK_IPP>,
722 <&cru HCLK_IPP>,
723 <&cru ACLK_RGA>,
724 <&cru HCLK_RGA>;
730 #power-domain-cells = <0>;
733 power-domain@RK3188_PD_VIDEO {
735 clocks = <&cru ACLK_VDPU>,
736 <&cru ACLK_VEPU>,
737 <&cru HCLK_VDPU>,
738 <&cru HCLK_VEPU>;
740 #power-domain-cells = <0>;
743 power-domain@RK3188_PD_GPU {
745 clocks = <&cru ACLK_GPU>;
747 #power-domain-cells = <0>;
753 pinctrl-names = "default";
754 pinctrl-0 = <&pwm0_out>;
758 pinctrl-names = "default";
759 pinctrl-0 = <&pwm1_out>;
763 pinctrl-names = "default";
764 pinctrl-0 = <&pwm2_out>;
768 pinctrl-names = "default";
769 pinctrl-0 = <&pwm3_out>;
773 compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi";
774 pinctrl-names = "default";
775 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
779 compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi";
780 pinctrl-names = "default";
781 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
785 compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart";
786 pinctrl-names = "default";
787 pinctrl-0 = <&uart0_xfer>;
791 compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart";
792 pinctrl-names = "default";
793 pinctrl-0 = <&uart1_xfer>;
797 compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart";
798 pinctrl-names = "default";
799 pinctrl-0 = <&uart2_xfer>;
803 compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart";
804 pinctrl-names = "default";
805 pinctrl-0 = <&uart3_xfer>;
809 compatible = "rockchip,rk3188-vpu", "rockchip,rk3066-vpu";
810 power-domains = <&power RK3188_PD_VIDEO>;
814 compatible = "rockchip,rk3188-wdt", "snps,dw-wdt";