Lines Matching +full:nfc +full:- +full:i2c
1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/clock/rk3128-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rk3128-power.h>
15 interrupt-parent = <&gic>;
16 #address-cells = <1>;
17 #size-cells = <1>;
33 arm-pmu {
34 compatible = "arm,cortex-a7-pmu";
39 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
43 #address-cells = <1>;
44 #size-cells = <0>;
45 enable-method = "rockchip,rk3036-smp";
49 compatible = "arm,cortex-a7";
51 clock-latency = <40000>;
54 operating-points-v2 = <&cpu_opp_table>;
55 #cooling-cells = <2>; /* min followed by max */
60 compatible = "arm,cortex-a7";
63 operating-points-v2 = <&cpu_opp_table>;
68 compatible = "arm,cortex-a7";
71 operating-points-v2 = <&cpu_opp_table>;
76 compatible = "arm,cortex-a7";
79 operating-points-v2 = <&cpu_opp_table>;
83 cpu_opp_table: opp-table-0 {
84 compatible = "operating-points-v2";
85 opp-shared;
87 opp-216000000 {
88 opp-hz = /bits/ 64 <216000000>;
89 opp-microvolt = <950000 950000 1325000>;
91 opp-408000000 {
92 opp-hz = /bits/ 64 <408000000>;
93 opp-microvolt = <950000 950000 1325000>;
95 opp-600000000 {
96 opp-hz = /bits/ 64 <600000000>;
97 opp-microvolt = <950000 950000 1325000>;
99 opp-696000000 {
100 opp-hz = /bits/ 64 <696000000>;
101 opp-microvolt = <975000 975000 1325000>;
103 opp-816000000 {
104 opp-hz = /bits/ 64 <816000000>;
105 opp-microvolt = <1075000 1075000 1325000>;
106 opp-suspend;
108 opp-1008000000 {
109 opp-hz = /bits/ 64 <1008000000>;
110 opp-microvolt = <1200000 1200000 1325000>;
112 opp-1200000000 {
113 opp-hz = /bits/ 64 <1200000000>;
114 opp-microvolt = <1325000 1325000 1325000>;
118 gpu_opp_table: opp-table-1 {
119 compatible = "operating-points-v2";
121 opp-200000000 {
122 opp-hz = /bits/ 64 <200000000>;
123 opp-microvolt = <975000 975000 1250000>;
125 opp-300000000 {
126 opp-hz = /bits/ 64 <300000000>;
127 opp-microvolt = <1050000 1050000 1250000>;
129 opp-400000000 {
130 opp-hz = /bits/ 64 <400000000>;
131 opp-microvolt = <1150000 1150000 1250000>;
133 opp-480000000 {
134 opp-hz = /bits/ 64 <480000000>;
135 opp-microvolt = <1250000 1250000 1250000>;
140 compatible = "arm,armv7-timer";
145 arm,cpu-registers-not-fw-configured;
146 clock-frequency = <24000000>;
150 compatible = "fixed-clock";
151 clock-frequency = <24000000>;
152 clock-output-names = "xin24m";
153 #clock-cells = <0>;
157 compatible = "mmio-sram";
159 #address-cells = <1>;
160 #size-cells = <1>;
163 smp-sram@0 {
164 compatible = "rockchip,rk3066-smp-sram";
170 compatible = "rockchip,rk3128-mali", "arm,mali-400";
178 interrupt-names = "gp",
185 clock-names = "bus", "core";
186 operating-points-v2 = <&gpu_opp_table>;
188 power-domains = <&power RK3128_PD_GPU>;
193 compatible = "rockchip,rk3128-pmu", "syscon", "simple-mfd";
196 power: power-controller {
197 compatible = "rockchip,rk3128-power-controller";
198 #power-domain-cells = <1>;
199 #address-cells = <1>;
200 #size-cells = <0>;
202 power-domain@RK3128_PD_VIO {
226 #power-domain-cells = <0>;
229 power-domain@RK3128_PD_VIDEO {
237 #power-domain-cells = <0>;
240 power-domain@RK3128_PD_GPU {
244 #power-domain-cells = <0>;
250 compatible = "rockchip,rk3128-qos", "syscon";
255 compatible = "rockchip,rk3128-qos", "syscon";
260 compatible = "rockchip,rk3128-qos", "syscon";
265 compatible = "rockchip,rk3128-qos", "syscon";
270 compatible = "rockchip,rk3128-qos", "syscon";
275 compatible = "rockchip,rk3128-qos", "syscon";
280 compatible = "rockchip,rk3128-qos", "syscon";
284 gic: interrupt-controller@10139000 {
285 compatible = "arm,cortex-a7-gic";
291 interrupt-controller;
292 #interrupt-cells = <3>;
293 #address-cells = <0>;
297 compatible = "rockchip,rk3128-usb", "rockchip,rk3066-usb", "snps,dwc2";
301 clock-names = "otg";
303 g-np-tx-fifo-size = <16>;
304 g-rx-fifo-size = <280>;
305 g-tx-fifo-size = <256 128 128 64 32 16>;
307 phy-names = "usb2-phy";
312 compatible = "generic-ehci";
317 phy-names = "usb";
322 compatible = "generic-ohci";
327 phy-names = "usb";
332 compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc";
337 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
339 dma-names = "rx-tx";
340 fifo-depth = <256>;
341 max-frequency = <150000000>;
343 reset-names = "reset";
348 compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc";
353 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
355 dma-names = "rx-tx";
356 fifo-depth = <256>;
357 max-frequency = <150000000>;
359 reset-names = "reset";
364 compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc";
369 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
371 dma-names = "rx-tx";
372 fifo-depth = <256>;
373 max-frequency = <150000000>;
375 reset-names = "reset";
379 nfc: nand-controller@10500000 {
380 compatible = "rockchip,rk3128-nfc", "rockchip,rk2928-nfc";
384 clock-names = "ahb", "nfc";
385 pinctrl-names = "default";
386 pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_cs0
391 cru: clock-controller@20000000 {
392 compatible = "rockchip,rk3128-cru";
395 clock-names = "xin24m";
397 #clock-cells = <1>;
398 #reset-cells = <1>;
399 assigned-clocks = <&cru PLL_GPLL>;
400 assigned-clock-rates = <594000000>;
404 compatible = "rockchip,rk3128-grf", "syscon", "simple-mfd";
406 #address-cells = <1>;
407 #size-cells = <1>;
410 compatible = "rockchip,rk3128-usb2phy";
413 clock-names = "phyclk";
414 clock-output-names = "usb480m_phy";
415 assigned-clocks = <&cru SCLK_USB480M>;
416 assigned-clock-parents = <&usb2phy>;
417 #clock-cells = <0>;
420 usb2phy_host: host-port {
422 interrupt-names = "linestate";
423 #phy-cells = <0>;
427 usb2phy_otg: otg-port {
431 interrupt-names = "otg-bvalid", "otg-id",
433 #phy-cells = <0>;
440 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer";
444 clock-names = "pclk", "timer";
448 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer";
452 clock-names = "pclk", "timer";
456 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer";
460 clock-names = "pclk", "timer";
464 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer";
468 clock-names = "pclk", "timer";
472 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer";
476 clock-names = "pclk", "timer";
480 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer";
484 clock-names = "pclk", "timer";
488 compatible = "rockchip,rk3128-wdt", "snps,dw-wdt";
496 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm";
499 pinctrl-names = "default";
500 pinctrl-0 = <&pwm0_pin>;
501 #pwm-cells = <3>;
506 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm";
509 pinctrl-names = "default";
510 pinctrl-0 = <&pwm1_pin>;
511 #pwm-cells = <3>;
516 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm";
519 pinctrl-names = "default";
520 pinctrl-0 = <&pwm2_pin>;
521 #pwm-cells = <3>;
526 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm";
529 pinctrl-names = "default";
530 pinctrl-0 = <&pwm3_pin>;
531 #pwm-cells = <3>;
535 i2c1: i2c@20056000 {
536 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c";
539 clock-names = "i2c";
541 pinctrl-names = "default";
542 pinctrl-0 = <&i2c1_xfer>;
543 #address-cells = <1>;
544 #size-cells = <0>;
548 i2c2: i2c@2005a000 {
549 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c";
552 clock-names = "i2c";
554 pinctrl-names = "default";
555 pinctrl-0 = <&i2c2_xfer>;
556 #address-cells = <1>;
557 #size-cells = <0>;
561 i2c3: i2c@2005e000 {
562 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c";
565 clock-names = "i2c";
567 pinctrl-names = "default";
568 pinctrl-0 = <&i2c3_xfer>;
569 #address-cells = <1>;
570 #size-cells = <0>;
575 compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart";
578 clock-frequency = <24000000>;
580 clock-names = "baudclk", "apb_pclk";
582 dma-names = "tx", "rx";
583 pinctrl-names = "default";
584 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
585 reg-io-width = <4>;
586 reg-shift = <2>;
591 compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart";
594 clock-frequency = <24000000>;
596 clock-names = "baudclk", "apb_pclk";
598 dma-names = "tx", "rx";
599 pinctrl-names = "default";
600 pinctrl-0 = <&uart1_xfer>;
601 reg-io-width = <4>;
602 reg-shift = <2>;
607 compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart";
610 clock-frequency = <24000000>;
612 clock-names = "baudclk", "apb_pclk";
614 dma-names = "tx", "rx";
615 pinctrl-names = "default";
616 pinctrl-0 = <&uart2_xfer>;
617 reg-io-width = <4>;
618 reg-shift = <2>;
627 clock-names = "saradc", "apb_pclk";
629 reset-names = "saradc-apb";
630 #io-channel-cells = <1>;
634 i2c0: i2c@20072000 {
635 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c";
638 clock-names = "i2c";
640 pinctrl-names = "default";
641 pinctrl-0 = <&i2c0_xfer>;
642 #address-cells = <1>;
643 #size-cells = <0>;
648 compatible = "rockchip,rk3128-spi", "rockchip,rk3066-spi";
652 clock-names = "spiclk", "apb_pclk";
654 dma-names = "tx", "rx";
655 pinctrl-names = "default";
656 pinctrl-0 = <&spi0_tx &spi0_rx &spi0_clk &spi0_cs0 &spi0_cs1>;
657 #address-cells = <1>;
658 #size-cells = <0>;
662 pdma: dma-controller@20078000 {
667 arm,pl330-broken-no-flushp;
668 arm,pl330-periph-burst;
670 clock-names = "apb_pclk";
671 #dma-cells = <1>;
675 compatible = "rockchip,rk3128-gmac";
679 interrupt-names = "macirq", "eth_wake_irq";
684 clock-names = "stmmaceth",
689 reset-names = "stmmaceth";
691 rx-fifo-depth = <4096>;
692 tx-fifo-depth = <2048>;
696 compatible = "snps,dwmac-mdio";
697 #address-cells = <0x1>;
698 #size-cells = <0x0>;
703 compatible = "rockchip,rk3128-pinctrl";
705 #address-cells = <1>;
706 #size-cells = <1>;
710 compatible = "rockchip,gpio-bank";
714 gpio-controller;
715 #gpio-cells = <2>;
716 interrupt-controller;
717 #interrupt-cells = <2>;
721 compatible = "rockchip,gpio-bank";
725 gpio-controller;
726 #gpio-cells = <2>;
727 interrupt-controller;
728 #interrupt-cells = <2>;
732 compatible = "rockchip,gpio-bank";
736 gpio-controller;
737 #gpio-cells = <2>;
738 interrupt-controller;
739 #interrupt-cells = <2>;
743 compatible = "rockchip,gpio-bank";
747 gpio-controller;
748 #gpio-cells = <2>;
749 interrupt-controller;
750 #interrupt-cells = <2>;
753 pcfg_pull_default: pcfg-pull-default {
754 bias-pull-pin-default;
757 pcfg_pull_none: pcfg-pull-none {
758 bias-disable;
762 emmc_clk: emmc-clk {
766 emmc_cmd: emmc-cmd {
770 emmc_cmd1: emmc-cmd1 {
774 emmc_pwr: emmc-pwr {
778 emmc_bus1: emmc-bus1 {
782 emmc_bus4: emmc-bus4 {
789 emmc_bus8: emmc-bus8 {
802 rgmii_pins: rgmii-pins {
820 rmii_pins: rmii-pins {
835 hdmii2c_xfer: hdmii2c-xfer {
840 hdmi_hpd: hdmi-hpd {
844 hdmi_cec: hdmi-cec {
850 i2c0_xfer: i2c0-xfer {
857 i2c1_xfer: i2c1-xfer {
864 i2c2_xfer: i2c2-xfer {
871 i2c3_xfer: i2c3-xfer {
878 i2s_bus: i2s-bus {
887 i2s1_bus: i2s1-bus {
898 lcdc_dclk: lcdc-dclk {
902 lcdc_den: lcdc-den {
906 lcdc_hsync: lcdc-hsync {
910 lcdc_vsync: lcdc-vsync {
914 lcdc_rgb24: lcdc-rgb24 {
932 nfc {
933 flash_ale: flash-ale {
937 flash_cle: flash-cle {
941 flash_wrn: flash-wrn {
945 flash_rdn: flash-rdn {
949 flash_rdy: flash-rdy {
953 flash_cs0: flash-cs0 {
957 flash_dqs: flash-dqs {
961 flash_bus8: flash-bus8 {
974 pwm0_pin: pwm0-pin {
980 pwm1_pin: pwm1-pin {
986 pwm2_pin: pwm2-pin {
992 pwm3_pin: pwm3-pin {
998 sdio_clk: sdio-clk {
1002 sdio_cmd: sdio-cmd {
1006 sdio_pwren: sdio-pwren {
1010 sdio_bus4: sdio-bus4 {
1019 sdmmc_clk: sdmmc-clk {
1023 sdmmc_cmd: sdmmc-cmd {
1027 sdmmc_det: sdmmc-det {
1031 sdmmc_wp: sdmmc-wp {
1035 sdmmc_pwren: sdmmc-pwren {
1039 sdmmc_bus4: sdmmc-bus4 {
1048 spdif_tx: spdif-tx {
1054 spi0_clk: spi0-clk {
1058 spi0_cs0: spi0-cs0 {
1062 spi0_tx: spi0-tx {
1066 spi0_rx: spi0-rx {
1070 spi0_cs1: spi0-cs1 {
1074 spi1_clk: spi1-clk {
1078 spi1_cs0: spi1-cs0 {
1082 spi1_tx: spi1-tx {
1086 spi1_rx: spi1-rx {
1090 spi1_cs1: spi1-cs1 {
1094 spi2_clk: spi2-clk {
1098 spi2_cs0: spi2-cs0 {
1102 spi2_tx: spi2-tx {
1106 spi2_rx: spi2-rx {
1112 uart0_xfer: uart0-xfer {
1117 uart0_cts: uart0-cts {
1121 uart0_rts: uart0-rts {
1127 uart1_xfer: uart1-xfer {
1132 uart1_cts: uart1-cts {
1136 uart1_rts: uart1-rts {
1142 uart2_xfer: uart2-xfer {
1147 uart2_cts: uart2-cts {
1151 uart2_rts: uart2-rts {