Lines Matching full:cru
6 #include <dt-bindings/clock/rk3128-cru.h>
52 clocks = <&cru ARMCLK>;
53 resets = <&cru SRST_CORE0>;
62 resets = <&cru SRST_CORE1>;
70 resets = <&cru SRST_CORE2>;
78 resets = <&cru SRST_CORE3>;
184 clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;
187 resets = <&cru SRST_GPU>;
204 clocks = <&cru ACLK_CIF>,
205 <&cru HCLK_CIF>,
206 <&cru DCLK_EBC>,
207 <&cru HCLK_EBC>,
208 <&cru ACLK_IEP>,
209 <&cru HCLK_IEP>,
210 <&cru ACLK_LCDC0>,
211 <&cru HCLK_LCDC0>,
212 <&cru PCLK_MIPI>,
213 <&cru ACLK_RGA>,
214 <&cru HCLK_RGA>,
215 <&cru ACLK_VIO0>,
216 <&cru ACLK_VIO1>,
217 <&cru HCLK_VIO>,
218 <&cru HCLK_VIO_H2P>,
219 <&cru DCLK_VOP>,
220 <&cru SCLK_VOP>;
231 clocks = <&cru ACLK_VDPU>,
232 <&cru HCLK_VDPU>,
233 <&cru ACLK_VEPU>,
234 <&cru HCLK_VEPU>,
235 <&cru SCLK_HEVC_CORE>;
242 clocks = <&cru ACLK_GPU>;
300 clocks = <&cru HCLK_OTG>;
315 clocks = <&cru HCLK_HOST2>;
325 clocks = <&cru HCLK_HOST2>;
335 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
336 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
342 resets = <&cru SRST_SDMMC>;
351 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
352 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
358 resets = <&cru SRST_SDIO>;
367 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
368 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
374 resets = <&cru SRST_EMMC>;
383 clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>;
391 cru: clock-controller@20000000 {
392 compatible = "rockchip,rk3128-cru";
399 assigned-clocks = <&cru PLL_GPLL>;
412 clocks = <&cru SCLK_OTGPHY0>;
415 assigned-clocks = <&cru SCLK_USB480M>;
443 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER0>;
451 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER1>;
459 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER2>;
467 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER3>;
475 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER4>;
483 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER5>;
491 clocks = <&cru PCLK_WDT>;
498 clocks = <&cru PCLK_PWM>;
508 clocks = <&cru PCLK_PWM>;
518 clocks = <&cru PCLK_PWM>;
528 clocks = <&cru PCLK_PWM>;
540 clocks = <&cru PCLK_I2C1>;
553 clocks = <&cru PCLK_I2C2>;
566 clocks = <&cru PCLK_I2C3>;
579 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
595 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
611 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
626 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
628 resets = <&cru SRST_SARADC>;
639 clocks = <&cru PCLK_I2C0>;
651 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
669 clocks = <&cru ACLK_DMAC>;
680 clocks = <&cru SCLK_MAC>,
681 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
682 <&cru SCLK_MAC_REF>, <&cru SCLK_MAC_REFOUT>,
683 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
688 resets = <&cru SRST_GMAC>;
713 clocks = <&cru PCLK_GPIO0>;
724 clocks = <&cru PCLK_GPIO1>;
735 clocks = <&cru PCLK_GPIO2>;
746 clocks = <&cru PCLK_GPIO3>;