Lines Matching +full:pinctrl +full:- +full:3
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/pinctrl/rockchip.h>
9 #include <dt-bindings/clock/rk3066a-cru.h>
10 #include <dt-bindings/power/rk3066-power.h>
22 #address-cells = <1>;
23 #size-cells = <0>;
24 enable-method = "rockchip,rk3066-smp";
28 compatible = "arm,cortex-a9";
29 next-level-cache = <&L2>;
31 operating-points =
40 clock-latency = <40000>;
45 compatible = "arm,cortex-a9";
46 next-level-cache = <&L2>;
51 display-subsystem {
52 compatible = "rockchip,display-subsystem";
57 compatible = "mmio-sram";
59 #address-cells = <1>;
60 #size-cells = <1>;
63 smp-sram@0 {
64 compatible = "rockchip,rk3066-smp-sram";
70 compatible = "rockchip,rk3066-vop";
76 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
77 power-domains = <&power RK3066_PD_VIO>;
81 reset-names = "axi", "ahb", "dclk";
85 #address-cells = <1>;
86 #size-cells = <0>;
90 remote-endpoint = <&hdmi_in_vop0>;
96 compatible = "rockchip,rk3066-vop";
102 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
103 power-domains = <&power RK3066_PD_VIO>;
107 reset-names = "axi", "ahb", "dclk";
111 #address-cells = <1>;
112 #size-cells = <0>;
116 remote-endpoint = <&hdmi_in_vop1>;
122 compatible = "rockchip,rk3066-hdmi";
126 clock-names = "hclk";
127 pinctrl-names = "default";
128 pinctrl-0 = <&hdmii2c_xfer>, <&hdmi_hpd>;
129 power-domains = <&power RK3066_PD_VIO>;
134 #address-cells = <1>;
135 #size-cells = <0>;
139 #address-cells = <1>;
140 #size-cells = <0>;
144 remote-endpoint = <&vop0_out_hdmi>;
149 remote-endpoint = <&vop1_out_hdmi>;
160 compatible = "rockchip,rk3066-i2s";
163 pinctrl-names = "default";
164 pinctrl-0 = <&i2s0_bus>;
166 clock-names = "i2s_clk", "i2s_hclk";
168 dma-names = "tx", "rx";
169 rockchip,playback-channels = <8>;
170 rockchip,capture-channels = <2>;
171 #sound-dai-cells = <0>;
176 compatible = "rockchip,rk3066-i2s";
179 pinctrl-names = "default";
180 pinctrl-0 = <&i2s1_bus>;
182 clock-names = "i2s_clk", "i2s_hclk";
184 dma-names = "tx", "rx";
185 rockchip,playback-channels = <2>;
186 rockchip,capture-channels = <2>;
187 #sound-dai-cells = <0>;
192 compatible = "rockchip,rk3066-i2s";
195 pinctrl-names = "default";
196 pinctrl-0 = <&i2s2_bus>;
198 clock-names = "i2s_clk", "i2s_hclk";
200 dma-names = "tx", "rx";
201 rockchip,playback-channels = <2>;
202 rockchip,capture-channels = <2>;
203 #sound-dai-cells = <0>;
207 cru: clock-controller@20000000 {
208 compatible = "rockchip,rk3066a-cru";
211 clock-names = "xin24m";
213 #clock-cells = <1>;
214 #reset-cells = <1>;
215 assigned-clocks = <&cru PLL_CPLL>, <&cru PLL_GPLL>,
219 assigned-clock-rates = <400000000>, <594000000>,
226 compatible = "snps,dw-apb-timer";
230 clock-names = "timer", "pclk";
234 compatible = "rockchip,rk3066a-efuse";
236 #address-cells = <1>;
237 #size-cells = <1>;
239 clock-names = "pclk_efuse";
247 compatible = "snps,dw-apb-timer";
251 clock-names = "timer", "pclk";
255 compatible = "snps,dw-apb-timer";
259 clock-names = "timer", "pclk";
263 compatible = "rockchip,rk3066-tsadc";
266 clock-names = "saradc", "apb_pclk";
268 #io-channel-cells = <1>;
270 reset-names = "saradc-apb";
274 pinctrl: pinctrl {
275 compatible = "rockchip,rk3066a-pinctrl";
277 #address-cells = <1>;
278 #size-cells = <1>;
282 compatible = "rockchip,gpio-bank";
287 gpio-controller;
288 #gpio-cells = <2>;
290 interrupt-controller;
291 #interrupt-cells = <2>;
295 compatible = "rockchip,gpio-bank";
300 gpio-controller;
301 #gpio-cells = <2>;
303 interrupt-controller;
304 #interrupt-cells = <2>;
308 compatible = "rockchip,gpio-bank";
313 gpio-controller;
314 #gpio-cells = <2>;
316 interrupt-controller;
317 #interrupt-cells = <2>;
321 compatible = "rockchip,gpio-bank";
326 gpio-controller;
327 #gpio-cells = <2>;
329 interrupt-controller;
330 #interrupt-cells = <2>;
334 compatible = "rockchip,gpio-bank";
339 gpio-controller;
340 #gpio-cells = <2>;
342 interrupt-controller;
343 #interrupt-cells = <2>;
347 compatible = "rockchip,gpio-bank";
352 gpio-controller;
353 #gpio-cells = <2>;
355 interrupt-controller;
356 #interrupt-cells = <2>;
359 pcfg_pull_default: pcfg-pull-default {
360 bias-pull-pin-default;
363 pcfg_pull_none: pcfg-pull-none {
364 bias-disable;
368 emac_xfer: emac-xfer {
379 emac_mdio: emac-mdio {
386 emmc_clk: emmc-clk {
387 rockchip,pins = <3 RK_PD7 2 &pcfg_pull_default>;
390 emmc_cmd: emmc-cmd {
394 emmc_rst: emmc-rst {
400 * not accessible through pinctrl. Also they should've
402 * flash/emmc is the boot-device.
407 hdmi_hpd: hdmi-hpd {
411 hdmii2c_xfer: hdmii2c-xfer {
418 i2c0_xfer: i2c0-xfer {
425 i2c1_xfer: i2c1-xfer {
432 i2c2_xfer: i2c2-xfer {
433 rockchip,pins = <3 RK_PA0 1 &pcfg_pull_none>,
434 <3 RK_PA1 1 &pcfg_pull_none>;
439 i2c3_xfer: i2c3-xfer {
440 rockchip,pins = <3 RK_PA2 2 &pcfg_pull_none>,
441 <3 RK_PA3 2 &pcfg_pull_none>;
446 i2c4_xfer: i2c4-xfer {
447 rockchip,pins = <3 RK_PA4 1 &pcfg_pull_none>,
448 <3 RK_PA5 1 &pcfg_pull_none>;
453 pwm0_out: pwm0-out {
459 pwm1_out: pwm1-out {
465 pwm2_out: pwm2-out {
471 pwm3_out: pwm3-out {
477 spi0_clk: spi0-clk {
480 spi0_cs0: spi0-cs0 {
483 spi0_tx: spi0-tx {
486 spi0_rx: spi0-rx {
489 spi0_cs1: spi0-cs1 {
495 spi1_clk: spi1-clk {
498 spi1_cs0: spi1-cs0 {
501 spi1_rx: spi1-rx {
504 spi1_tx: spi1-tx {
507 spi1_cs1: spi1-cs1 {
513 uart0_xfer: uart0-xfer {
518 uart0_cts: uart0-cts {
522 uart0_rts: uart0-rts {
528 uart1_xfer: uart1-xfer {
533 uart1_cts: uart1-cts {
537 uart1_rts: uart1-rts {
543 uart2_xfer: uart2-xfer {
551 uart3_xfer: uart3-xfer {
552 rockchip,pins = <3 RK_PD3 1 &pcfg_pull_default>,
553 <3 RK_PD4 1 &pcfg_pull_default>;
556 uart3_cts: uart3-cts {
557 rockchip,pins = <3 RK_PD5 1 &pcfg_pull_default>;
560 uart3_rts: uart3-rts {
561 rockchip,pins = <3 RK_PD6 1 &pcfg_pull_default>;
566 sd0_clk: sd0-clk {
567 rockchip,pins = <3 RK_PB0 1 &pcfg_pull_default>;
570 sd0_cmd: sd0-cmd {
571 rockchip,pins = <3 RK_PB1 1 &pcfg_pull_default>;
574 sd0_cd: sd0-cd {
575 rockchip,pins = <3 RK_PB6 1 &pcfg_pull_default>;
578 sd0_wp: sd0-wp {
579 rockchip,pins = <3 RK_PB7 1 &pcfg_pull_default>;
582 sd0_bus1: sd0-bus-width1 {
583 rockchip,pins = <3 RK_PB2 1 &pcfg_pull_default>;
586 sd0_bus4: sd0-bus-width4 {
587 rockchip,pins = <3 RK_PB2 1 &pcfg_pull_default>,
588 <3 RK_PB3 1 &pcfg_pull_default>,
589 <3 RK_PB4 1 &pcfg_pull_default>,
590 <3 RK_PB5 1 &pcfg_pull_default>;
595 sd1_clk: sd1-clk {
596 rockchip,pins = <3 RK_PC5 1 &pcfg_pull_default>;
599 sd1_cmd: sd1-cmd {
600 rockchip,pins = <3 RK_PC0 1 &pcfg_pull_default>;
603 sd1_cd: sd1-cd {
604 rockchip,pins = <3 RK_PC6 1 &pcfg_pull_default>;
607 sd1_wp: sd1-wp {
608 rockchip,pins = <3 RK_PC7 1 &pcfg_pull_default>;
611 sd1_bus1: sd1-bus-width1 {
612 rockchip,pins = <3 RK_PC1 1 &pcfg_pull_default>;
615 sd1_bus4: sd1-bus-width4 {
616 rockchip,pins = <3 RK_PC1 1 &pcfg_pull_default>,
617 <3 RK_PC2 1 &pcfg_pull_default>,
618 <3 RK_PC3 1 &pcfg_pull_default>,
619 <3 RK_PC4 1 &pcfg_pull_default>;
624 i2s0_bus: i2s0-bus {
638 i2s1_bus: i2s1-bus {
649 i2s2_bus: i2s2-bus {
662 compatible = "rockchip,rk3066-mali", "arm,mali-400";
673 interrupt-names = "gp",
683 power-domains = <&power RK3066_PD_GPU>;
687 compatible = "rockchip,rk3066-grf", "syscon", "simple-mfd";
690 compatible = "rockchip,rk3066a-usb-phy";
691 #address-cells = <1>;
692 #size-cells = <0>;
695 usbphy0: usb-phy@17c {
698 clock-names = "phyclk";
699 #clock-cells = <0>;
700 #phy-cells = <0>;
703 usbphy1: usb-phy@188 {
706 clock-names = "phyclk";
707 #clock-cells = <0>;
708 #phy-cells = <0>;
714 pinctrl-names = "default";
715 pinctrl-0 = <&i2c0_xfer>;
719 pinctrl-names = "default";
720 pinctrl-0 = <&i2c1_xfer>;
724 pinctrl-names = "default";
725 pinctrl-0 = <&i2c2_xfer>;
729 pinctrl-names = "default";
730 pinctrl-0 = <&i2c3_xfer>;
734 pinctrl-names = "default";
735 pinctrl-0 = <&i2c4_xfer>;
739 clock-frequency = <50000000>;
741 dma-names = "rx-tx";
742 max-frequency = <50000000>;
743 pinctrl-names = "default";
744 pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4>;
748 dmas = <&dmac2 3>;
749 dma-names = "rx-tx";
750 pinctrl-names = "default";
751 pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_bus4>;
756 dma-names = "rx-tx";
760 power: power-controller {
761 compatible = "rockchip,rk3066-power-controller";
762 #power-domain-cells = <1>;
763 #address-cells = <1>;
764 #size-cells = <0>;
766 power-domain@RK3066_PD_VIO {
791 #power-domain-cells = <0>;
794 power-domain@RK3066_PD_VIDEO {
801 #power-domain-cells = <0>;
804 power-domain@RK3066_PD_GPU {
808 #power-domain-cells = <0>;
814 pinctrl-names = "default";
815 pinctrl-0 = <&pwm0_out>;
819 pinctrl-names = "default";
820 pinctrl-0 = <&pwm1_out>;
824 pinctrl-names = "default";
825 pinctrl-0 = <&pwm2_out>;
829 pinctrl-names = "default";
830 pinctrl-0 = <&pwm3_out>;
834 pinctrl-names = "default";
835 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
839 pinctrl-names = "default";
840 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
844 compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart";
846 dma-names = "tx", "rx";
847 pinctrl-names = "default";
848 pinctrl-0 = <&uart0_xfer>;
852 compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart";
853 dmas = <&dmac1_s 2>, <&dmac1_s 3>;
854 dma-names = "tx", "rx";
855 pinctrl-names = "default";
856 pinctrl-0 = <&uart1_xfer>;
860 compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart";
862 dma-names = "tx", "rx";
863 pinctrl-names = "default";
864 pinctrl-0 = <&uart2_xfer>;
868 compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart";
870 dma-names = "tx", "rx";
871 pinctrl-names = "default";
872 pinctrl-0 = <&uart3_xfer>;
876 power-domains = <&power RK3066_PD_VIDEO>;
880 compatible = "rockchip,rk3066-wdt", "snps,dw-wdt";
884 compatible = "rockchip,rk3066-emac";