Lines Matching full:cru
7 #include <dt-bindings/clock/rk3036-cru.h>
44 resets = <&cru SRST_CORE0>;
50 clocks = <&cru ARMCLK>;
57 resets = <&cru SRST_CORE1>;
114 assigned-clocks = <&cru SCLK_GPU>;
116 clocks = <&cru SCLK_GPU>, <&cru SCLK_GPU>;
119 resets = <&cru SRST_GPU>;
128 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
138 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
148 clocks = <&cru ACLK_LCDC>, <&cru SCLK_LCDC>, <&cru HCLK_LCDC>;
150 resets = <&cru SRST_LCDC1_A>, <&cru SRST_LCDC1_H>, <&cru SRST_LCDC1_D>;
170 clocks = <&cru ACLK_LCDC>, <&cru HCLK_LCDC>;
210 clocks = <&cru HCLK_OTG0>;
224 clocks = <&cru HCLK_OTG1>;
235 clocks = <&cru HCLK_MAC>, <&cru SCLK_MACREF>, <&cru SCLK_MAC>;
242 assigned-clocks = <&cru SCLK_MACPLL>;
243 assigned-clock-parents = <&cru PLL_DPLL>;
254 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
258 resets = <&cru SRST_MMC0>;
267 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
268 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
272 resets = <&cru SRST_SDIO>;
285 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
286 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
296 resets = <&cru SRST_EMMC>;
306 clocks = <&cru SCLK_I2S>, <&cru HCLK_I2S>;
320 clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>;
322 assigned-clocks = <&cru SCLK_NANDC>;
330 cru: clock-controller@20000000 {
331 compatible = "rockchip,rk3036-cru";
338 assigned-clocks = <&cru PLL_GPLL>;
354 clocks = <&cru ACLK_LCDC>,
355 <&cru HCLK_LCDC>,
356 <&cru SCLK_LCDC>;
363 clocks = <&cru ACLK_VCODEC>,
364 <&cru HCLK_VCODEC>;
371 clocks = <&cru SCLK_GPU>;
392 clocks = <&cru PCLK_ACODEC>;
400 clocks = <&cru PCLK_HDMI>;
429 clocks = <&cru PCLK_TIMER>, <&xin24m>;
437 clocks = <&cru PCLK_PWM>;
447 clocks = <&cru PCLK_PWM>;
457 clocks = <&cru PCLK_PWM>;
467 clocks = <&cru PCLK_PWM>;
480 clocks = <&cru PCLK_I2C1>;
493 clocks = <&cru PCLK_I2C2>;
506 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
520 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
534 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
548 clocks = <&cru PCLK_I2C0>;
558 clocks = <&cru PCLK_SPI>, <&cru SCLK_SPI>;
577 clocks = <&cru ACLK_DMAC2>;
592 clocks = <&cru PCLK_GPIO0>;
605 clocks = <&cru PCLK_GPIO1>;
618 clocks = <&cru PCLK_GPIO2>;