Lines Matching +full:0 +full:xfb400000
20 #size-cells = <0>;
22 cpu0: cpu@0 {
25 reg = <0>;
44 reg = <0xf0000200 0x100>;
51 reg = <0xf0000600 0x20>;
60 reg = <0xf0001000 0x1000>,
61 <0xf0000100 0x100>;
66 reg = <0xf0100000 0x1000>;
78 reg = <0xfb400000 0x400>;
87 reg = <0xfe400000 0x400>;
103 reg = <0xe6138000 0x200>;
115 reg = <0xe6900000 4>,
116 <0xe6900010 4>,
117 <0xe6900020 1>,
118 <0xe6900040 1>,
119 <0xe6900060 1>;
137 reg = <0xe6900004 4>,
138 <0xe6900014 4>,
139 <0xe6900024 1>,
140 <0xe6900044 1>,
141 <0xe6900064 1>;
159 reg = <0xe6900008 4>,
160 <0xe6900018 4>,
161 <0xe6900028 1>,
162 <0xe6900048 1>,
163 <0xe6900068 1>;
181 reg = <0xe690000c 4>,
182 <0xe690001c 4>,
183 <0xe690002c 1>,
184 <0xe690004c 1>,
185 <0xe690006c 1>;
201 #size-cells = <0>;
203 reg = <0xe6820000 0x425>;
215 #size-cells = <0>;
217 reg = <0xe6822000 0x425>;
229 #size-cells = <0>;
231 reg = <0xe6824000 0x425>;
243 #size-cells = <0>;
245 reg = <0xe6826000 0x425>;
257 #size-cells = <0>;
259 reg = <0xe6828000 0x425>;
271 reg = <0xe6bd0000 0x100>;
282 reg = <0xe6e20000 0x0064>;
287 #size-cells = <0>;
293 reg = <0xe6e10000 0x0064>;
298 #size-cells = <0>;
304 reg = <0xe6e00000 0x0064>;
309 #size-cells = <0>;
315 reg = <0xe6c90000 0x0064>;
320 #size-cells = <0>;
326 reg = <0xee100000 0x100>;
339 reg = <0xee120000 0x100>;
351 reg = <0xee140000 0x100>;
363 reg = <0xe6c40000 0x100>;
373 reg = <0xe6c50000 0x100>;
383 reg = <0xe6c60000 0x100>;
393 reg = <0xe6c70000 0x100>;
403 reg = <0xe6c80000 0x100>;
413 reg = <0xe6cb0000 0x100>;
423 reg = <0xe6cc0000 0x100>;
433 reg = <0xe6cd0000 0x100>;
443 reg = <0xe6c30000 0x100>;
453 reg = <0xe6050000 0x8000>,
454 <0xe605801c 0x1c>;
458 <&pfc 0 0 119>, <&pfc 128 128 37>, <&pfc 192 192 91>,
461 <&irqpin0 0 0>, <&irqpin0 1 0>, <&irqpin0 2 0>, <&irqpin0 3 0>,
462 <&irqpin0 4 0>, <&irqpin0 5 0>, <&irqpin0 6 0>, <&irqpin0 7 0>,
463 <&irqpin1 0 0>, <&irqpin1 1 0>, <&irqpin1 2 0>, <&irqpin1 3 0>,
464 <&irqpin1 4 0>, <&irqpin1 5 0>, <&irqpin1 6 0>, <&irqpin1 7 0>,
465 <&irqpin2 0 0>, <&irqpin2 1 0>, <&irqpin2 2 0>, <&irqpin2 3 0>,
466 <&irqpin2 4 0>, <&irqpin2 5 0>, <&irqpin2 6 0>, <&irqpin2 7 0>,
467 <&irqpin3 0 0>, <&irqpin3 1 0>, <&irqpin3 2 0>, <&irqpin3 3 0>,
468 <&irqpin3 4 0>, <&irqpin3 5 0>, <&irqpin3 6 0>, <&irqpin3 7 0>;
474 reg = <0xe6180000 0x8000>, <0xe6188000 0x8000>;
479 #size-cells = <0>;
480 #power-domain-cells = <0>;
482 pd_c4: c4@0 {
483 reg = <0>;
484 #power-domain-cells = <0>;
489 #power-domain-cells = <0>;
494 #power-domain-cells = <0>;
499 #power-domain-cells = <0>;
504 #power-domain-cells = <0>;
509 #power-domain-cells = <0>;
515 #size-cells = <0>;
516 #power-domain-cells = <0>;
520 #power-domain-cells = <0>;
525 #power-domain-cells = <0>;
532 #size-cells = <0>;
533 #power-domain-cells = <0>;
538 #size-cells = <0>;
539 #power-domain-cells = <0>;
544 #size-cells = <0>;
545 #power-domain-cells = <0>;
553 #size-cells = <0>;
554 #power-domain-cells = <0>;
558 #power-domain-cells = <0>;
563 #power-domain-cells = <0>;
569 #size-cells = <0>;
570 #power-domain-cells = <0>;
574 #power-domain-cells = <0>;
585 reg = <0xec230000 0x400>;
586 interrupts = <GIC_SPI 146 0x4>;
597 ranges = <0 0 0x20000000>;
598 reg = <0xfec10000 0x400>;
612 #clock-cells = <0>;
617 #clock-cells = <0>;
622 #clock-cells = <0>;
624 clock-frequency = <0>;
628 #clock-cells = <0>;
630 clock-frequency = <0>;
634 #clock-cells = <0>;
636 clock-frequency = <0>;
640 #clock-cells = <0>;
642 clock-frequency = <0>;
648 reg = <0xe6150000 0x10000>;
660 reg = <0xe6150008 4>;
664 <0>;
665 #clock-cells = <0>;
669 reg = <0xe615000c 4>;
673 <0>;
674 #clock-cells = <0>;
678 reg = <0xe615001c 4>;
682 <0>;
683 #clock-cells = <0>;
687 reg = <0xe6150010 4>;
688 clocks = <&pll1_div2_clk>, <0>,
689 <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
690 #clock-cells = <0>;
695 reg = <0xe6150014 4>;
696 clocks = <&pll1_div2_clk>, <0>,
697 <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
698 #clock-cells = <0>;
702 reg = <0xe6150074 4>;
704 <&pll1_div13_clk>, <0>;
705 #clock-cells = <0>;
709 reg = <0xe6150078 4>;
711 <&pll1_div13_clk>, <0>;
712 #clock-cells = <0>;
716 reg = <0xe615007c 4>;
718 <&pll1_div13_clk>, <0>;
719 #clock-cells = <0>;
723 reg = <0xe6150018 4>;
726 #clock-cells = <0>;
730 reg = <0xe6150090 4>;
733 #clock-cells = <0>;
737 reg = <0xe6150080 4>;
740 #clock-cells = <0>;
744 reg = <0xe6150084 4>;
747 #clock-cells = <0>;
751 reg = <0xe6150094 4>;
754 #clock-cells = <0>;
758 reg = <0xe6150088 4>;
759 clocks = <&pll1_div2_clk>, <0>,
760 <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
761 #clock-cells = <0>;
765 reg = <0xe615008c 4>;
767 <&pll1_div7_clk>, <0>;
768 #clock-cells = <0>;
772 reg = <0xe6150098 4>;
773 clocks = <&pll1_div2_clk>, <0>,
774 <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
775 #clock-cells = <0>;
779 reg = <0xe615009c 4>;
780 clocks = <&pll1_div2_clk>, <0>,
781 <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
782 #clock-cells = <0>;
786 reg = <0xe6150060 4>;
787 clocks = <&pll1_div2_clk>, <0>,
788 <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
789 #clock-cells = <0>;
793 reg = <0xe6150064 4>;
796 <&extcki_clk>, <0>, <0>, <0>;
797 #clock-cells = <0>;
804 #clock-cells = <0>;
811 #clock-cells = <0>;
818 #clock-cells = <0>;
825 #clock-cells = <0>;
832 #clock-cells = <0>;
840 reg = <0xe6150130 4>, <0xe6150030 4>;
851 reg = <0xe6150134 4>, <0xe6150038 4>;
874 reg = <0xe6150138 4>, <0xe6150040 4>;
898 reg = <0xe615013c 4>, <0xe6150048 4>;
926 reg = <0xe6150140 4>, <0xe615004c 4>;
939 reg = <0xe6150144 4>, <0xe615003c 4>;