Lines Matching +full:0 +full:xe6180000
40 #clock-cells = <0>;
42 clock-frequency = <0>;
47 #size-cells = <0>;
49 cpu0: cpu@0 {
52 reg = <0>;
71 L2_CA15: cache-controller-0 {
82 #clock-cells = <0>;
84 clock-frequency = <0>;
91 ranges = <0 0 0 0x1c000000>;
104 #clock-cells = <0>;
106 clock-frequency = <0>;
120 reg = <0 0xe6020000 0 0x0c>;
131 reg = <0 0xe6050000 0 0x50>;
135 gpio-ranges = <&pfc 0 0 29>;
146 reg = <0 0xe6051000 0 0x50>;
150 gpio-ranges = <&pfc 0 32 23>;
161 reg = <0 0xe6052000 0 0x50>;
165 gpio-ranges = <&pfc 0 64 32>;
176 reg = <0 0xe6053000 0 0x50>;
180 gpio-ranges = <&pfc 0 96 28>;
191 reg = <0 0xe6054000 0 0x50>;
195 gpio-ranges = <&pfc 0 128 17>;
206 reg = <0 0xe6055000 0 0x50>;
210 gpio-ranges = <&pfc 0 160 17>;
221 reg = <0 0xe6055100 0 0x50>;
225 gpio-ranges = <&pfc 0 192 17>;
236 reg = <0 0xe6055200 0 0x50>;
240 gpio-ranges = <&pfc 0 224 17>;
251 reg = <0 0xe6055300 0 0x50>;
255 gpio-ranges = <&pfc 0 256 17>;
266 reg = <0 0xe6055400 0 0x50>;
270 gpio-ranges = <&pfc 0 288 17>;
281 reg = <0 0xe6055500 0 0x50>;
285 gpio-ranges = <&pfc 0 320 32>;
296 reg = <0 0xe6055600 0 0x50>;
300 gpio-ranges = <&pfc 0 352 30>;
310 reg = <0 0xe6060000 0 0x144>;
315 reg = <0 0xe6150000 0 0x1000>;
319 #power-domain-cells = <0>;
325 reg = <0 0xe6152000 0 0x188>;
331 reg = <0 0xe6160000 0 0x0100>;
336 reg = <0 0xe6180000 0 0x0200>;
344 reg = <0 0xe61c0000 0 0x200>;
345 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
356 reg = <0 0xe63a0000 0 0x12000>;
359 ranges = <0 0 0xe63a0000 0x12000>;
364 reg = <0 0xe63c0000 0 0x1000>;
367 ranges = <0 0 0xe63c0000 0x1000>;
369 smp-sram@0 {
371 reg = <0 0x100>;
379 reg = <0 0xe6508000 0 0x40>;
386 #size-cells = <0>;
393 reg = <0 0xe6518000 0 0x40>;
400 #size-cells = <0>;
407 reg = <0 0xe6530000 0 0x40>;
414 #size-cells = <0>;
421 reg = <0 0xe6540000 0 0x40>;
428 #size-cells = <0>;
435 reg = <0 0xe6520000 0 0x40>;
442 #size-cells = <0>;
449 reg = <0 0xe6528000 0 0x40>;
456 #size-cells = <0>;
462 #size-cells = <0>;
466 reg = <0 0xe60b0000 0 0x425>;
469 dmas = <&dmac0 0x77>, <&dmac0 0x78>,
470 <&dmac1 0x77>, <&dmac1 0x78>;
480 reg = <0 0xe6700000 0 0x20000>;
513 reg = <0 0xe6720000 0 0x20000>;
546 reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
553 #size-cells = <0>;
559 reg = <0 0xe6b10000 0 0x2c>;
562 dmas = <&dmac0 0x17>, <&dmac0 0x18>,
563 <&dmac1 0x17>, <&dmac1 0x18>;
569 #size-cells = <0>;
576 reg = <0 0xe6e60000 0 64>;
581 dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
582 <&dmac1 0x29>, <&dmac1 0x2a>;
592 reg = <0 0xe6e68000 0 64>;
597 dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
598 <&dmac1 0x2d>, <&dmac1 0x2e>;
608 reg = <0 0xe6e58000 0 64>;
613 dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
614 <&dmac1 0x2b>, <&dmac1 0x2c>;
624 reg = <0 0xe6ea8000 0 64>;
629 dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
630 <&dmac1 0x2f>, <&dmac1 0x30>;
640 reg = <0 0xe62c0000 0 96>;
645 dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
646 <&dmac1 0x39>, <&dmac1 0x3a>;
656 reg = <0 0xe62c8000 0 96>;
661 dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
662 <&dmac1 0x4d>, <&dmac1 0x4e>;
672 reg = <0 0xe6e20000 0 0x0064>;
675 dmas = <&dmac0 0x51>, <&dmac0 0x52>,
676 <&dmac1 0x51>, <&dmac1 0x52>;
681 #size-cells = <0>;
688 reg = <0 0xe6e10000 0 0x0064>;
691 dmas = <&dmac0 0x55>, <&dmac0 0x56>,
692 <&dmac1 0x55>, <&dmac1 0x56>;
697 #size-cells = <0>;
704 reg = <0 0xe6e80000 0 0x1000>;
717 reg = <0 0xe6e88000 0 0x1000>;
730 reg = <0 0xe6ef0000 0 0x1000>;
741 reg = <0 0xe6ef1000 0 0x1000>;
752 reg = <0 0xe6ef2000 0 0x1000>;
763 reg = <0 0xe6ef3000 0 0x1000>;
774 reg = <0 0xe6ef4000 0 0x1000>;
785 reg = <0 0xe6ef5000 0 0x1000>;
796 reg = <0 0xee100000 0 0x328>;
797 interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
798 dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
799 <&dmac1 0xcd>, <&dmac1 0xce>;
811 reg = <0 0xf1001000 0 0x1000>,
812 <0 0xf1002000 0 0x2000>,
813 <0 0xf1004000 0 0x2000>,
814 <0 0xf1006000 0 0x2000>;
825 reg = <0 0xfe928000 0 0x8000>;
834 reg = <0 0xfe930000 0 0x8000>;
843 reg = <0 0xfe938000 0 0x8000>;
853 reg = <0 0xfe980000 0 0x10300>;
862 reg = <0 0xfeb00000 0 0x40000>;
866 clock-names = "du.0", "du.1";
868 reset-names = "du.0";
873 #size-cells = <0>;
875 port@0 {
876 reg = <0>;
890 reg = <0 0xff000044 0 4>;
896 reg = <0 0xffca0000 0 0x1004>;
910 reg = <0 0xe6130000 0 0x1004>;