Lines Matching full:cpg
8 #include <dt-bindings/clock/r8a7742-cpg-mssr.h>
56 clocks = <&cpg CPG_CORE R8A7742_CLK_Z>;
78 clocks = <&cpg CPG_CORE R8A7742_CLK_Z>;
100 clocks = <&cpg CPG_CORE R8A7742_CLK_Z>;
122 clocks = <&cpg CPG_CORE R8A7742_CLK_Z>;
144 clocks = <&cpg CPG_CORE R8A7742_CLK_Z2>;
154 clocks = <&cpg CPG_CORE R8A7742_CLK_Z2>;
164 clocks = <&cpg CPG_CORE R8A7742_CLK_Z2>;
174 clocks = <&cpg CPG_CORE R8A7742_CLK_Z2>;
248 clocks = <&cpg CPG_MOD 402>;
250 resets = <&cpg 402>;
264 clocks = <&cpg CPG_MOD 912>;
266 resets = <&cpg 912>;
279 clocks = <&cpg CPG_MOD 911>;
281 resets = <&cpg 911>;
294 clocks = <&cpg CPG_MOD 910>;
296 resets = <&cpg 910>;
309 clocks = <&cpg CPG_MOD 909>;
311 resets = <&cpg 909>;
324 clocks = <&cpg CPG_MOD 908>;
326 resets = <&cpg 908>;
339 clocks = <&cpg CPG_MOD 907>;
341 resets = <&cpg 907>;
353 clocks = <&cpg CPG_MOD 304>;
355 resets = <&cpg 304>;
360 cpg: clock-controller@e6150000 { label
361 compatible = "renesas,r8a7742-cpg-mssr";
402 clocks = <&cpg CPG_MOD 407>;
404 resets = <&cpg 407>;
414 clocks = <&cpg CPG_MOD 125>;
417 resets = <&cpg 125>;
429 clocks = <&cpg CPG_MOD 111>;
432 resets = <&cpg 111>;
444 clocks = <&cpg CPG_MOD 122>;
447 resets = <&cpg 122>;
458 clocks = <&cpg CPG_MOD 121>;
461 resets = <&cpg 121>;
470 clocks = <&cpg CPG_MOD 522>;
472 resets = <&cpg 522>;
560 clocks = <&cpg CPG_MOD 931>;
562 resets = <&cpg 931>;
574 clocks = <&cpg CPG_MOD 930>;
576 resets = <&cpg 930>;
588 clocks = <&cpg CPG_MOD 929>;
590 resets = <&cpg 929>;
602 clocks = <&cpg CPG_MOD 928>;
604 resets = <&cpg 928>;
617 clocks = <&cpg CPG_MOD 318>;
622 resets = <&cpg 318>;
634 clocks = <&cpg CPG_MOD 323>;
639 resets = <&cpg 323>;
651 clocks = <&cpg CPG_MOD 300>;
656 resets = <&cpg 300>;
668 clocks = <&cpg CPG_MOD 926>;
673 resets = <&cpg 926>;
682 clocks = <&cpg CPG_MOD 704>;
687 resets = <&cpg 704>;
700 clocks = <&cpg CPG_MOD 704>;
703 resets = <&cpg 704>;
723 clocks = <&cpg CPG_MOD 330>;
725 resets = <&cpg 330>;
737 clocks = <&cpg CPG_MOD 331>;
739 resets = <&cpg 331>;
769 clocks = <&cpg CPG_MOD 219>;
772 resets = <&cpg 219>;
802 clocks = <&cpg CPG_MOD 218>;
805 resets = <&cpg 218>;
815 clocks = <&cpg CPG_MOD 812>;
818 resets = <&cpg 812>;
828 clocks = <&cpg CPG_MOD 917>;
833 resets = <&cpg 917>;
845 clocks = <&cpg CPG_MOD 204>;
851 resets = <&cpg 204>;
860 clocks = <&cpg CPG_MOD 203>;
866 resets = <&cpg 203>;
875 clocks = <&cpg CPG_MOD 202>;
881 resets = <&cpg 202>;
890 clocks = <&cpg CPG_MOD 206>;
896 resets = <&cpg 206>;
905 clocks = <&cpg CPG_MOD 207>;
911 resets = <&cpg 207>;
920 clocks = <&cpg CPG_MOD 216>;
926 resets = <&cpg 216>;
935 clocks = <&cpg CPG_MOD 721>,
936 <&cpg CPG_CORE R8A7742_CLK_ZS>, <&scif_clk>;
942 resets = <&cpg 721>;
951 clocks = <&cpg CPG_MOD 720>,
952 <&cpg CPG_CORE R8A7742_CLK_ZS>, <&scif_clk>;
958 resets = <&cpg 720>;
967 clocks = <&cpg CPG_MOD 310>,
968 <&cpg CPG_CORE R8A7742_CLK_ZS>, <&scif_clk>;
974 resets = <&cpg 310>;
983 clocks = <&cpg CPG_MOD 717>,
984 <&cpg CPG_CORE R8A7742_CLK_ZS>, <&scif_clk>;
990 resets = <&cpg 717>;
999 clocks = <&cpg CPG_MOD 716>,
1000 <&cpg CPG_CORE R8A7742_CLK_ZS>, <&scif_clk>;
1006 resets = <&cpg 716>;
1015 clocks = <&cpg CPG_MOD 0>;
1020 resets = <&cpg 0>;
1031 clocks = <&cpg CPG_MOD 208>;
1036 resets = <&cpg 208>;
1047 clocks = <&cpg CPG_MOD 205>;
1052 resets = <&cpg 205>;
1063 clocks = <&cpg CPG_MOD 215>;
1068 resets = <&cpg 215>;
1079 clocks = <&cpg CPG_MOD 916>,
1080 <&cpg CPG_CORE R8A7742_CLK_RCAN>, <&can_clk>;
1083 resets = <&cpg 916>;
1092 clocks = <&cpg CPG_MOD 915>,
1093 <&cpg CPG_CORE R8A7742_CLK_RCAN>, <&can_clk>;
1096 resets = <&cpg 915>;
1103 clocks = <&cpg CPG_MOD 523>;
1105 resets = <&cpg 523>;
1113 clocks = <&cpg CPG_MOD 523>;
1115 resets = <&cpg 523>;
1123 clocks = <&cpg CPG_MOD 523>;
1125 resets = <&cpg 523>;
1133 clocks = <&cpg CPG_MOD 523>;
1135 resets = <&cpg 523>;
1143 clocks = <&cpg CPG_MOD 523>;
1145 resets = <&cpg 523>;
1153 clocks = <&cpg CPG_MOD 523>;
1155 resets = <&cpg 523>;
1163 clocks = <&cpg CPG_MOD 523>;
1165 resets = <&cpg 523>;
1175 clocks = <&cpg CPG_MOD 811>;
1177 resets = <&cpg 811>;
1186 clocks = <&cpg CPG_MOD 810>;
1188 resets = <&cpg 810>;
1197 clocks = <&cpg CPG_MOD 809>;
1199 resets = <&cpg 809>;
1208 clocks = <&cpg CPG_MOD 808>;
1210 resets = <&cpg 808>;
1230 clocks = <&cpg CPG_MOD 1005>,
1231 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
1232 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
1233 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
1234 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
1235 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
1236 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
1237 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
1238 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
1239 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
1240 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
1241 <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>,
1242 <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>,
1243 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
1245 <&cpg CPG_CORE R8A7742_CLK_M2>;
1258 resets = <&cpg 1005>,
1259 <&cpg 1006>, <&cpg 1007>,
1260 <&cpg 1008>, <&cpg 1009>,
1261 <&cpg 1010>, <&cpg 1011>,
1262 <&cpg 1012>, <&cpg 1013>,
1263 <&cpg 1014>, <&cpg 1015>;
1438 clocks = <&cpg CPG_MOD 502>;
1441 resets = <&cpg 502>;
1469 clocks = <&cpg CPG_MOD 501>;
1472 resets = <&cpg 501>;
1482 clocks = <&cpg CPG_MOD 328>;
1484 resets = <&cpg 328>;
1497 clocks = <&cpg CPG_MOD 703>;
1499 resets = <&cpg 703>;
1532 clocks = <&cpg CPG_MOD 703>;
1534 resets = <&cpg 703>;
1552 clocks = <&cpg CPG_MOD 703>;
1554 resets = <&cpg 703>;
1588 clocks = <&cpg CPG_MOD 314>;
1594 resets = <&cpg 314>;
1603 clocks = <&cpg CPG_MOD 313>;
1609 resets = <&cpg 313>;
1618 clocks = <&cpg CPG_MOD 312>;
1624 resets = <&cpg 312>;
1633 clocks = <&cpg CPG_MOD 311>;
1639 resets = <&cpg 311>;
1648 clocks = <&cpg CPG_MOD 315>;
1653 resets = <&cpg 315>;
1664 clocks = <&cpg CPG_MOD 305>;
1669 resets = <&cpg 305>;
1680 clocks = <&cpg CPG_MOD 815>;
1682 resets = <&cpg 815>;
1691 clocks = <&cpg CPG_MOD 814>;
1693 resets = <&cpg 814>;
1702 clocks = <&cpg CPG_MOD 813>;
1704 resets = <&cpg 813>;
1719 clocks = <&cpg CPG_MOD 408>;
1722 resets = <&cpg 408>;
1746 clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
1749 resets = <&cpg 319>;
1757 clocks = <&cpg CPG_MOD 130>;
1759 resets = <&cpg 130>;
1766 clocks = <&cpg CPG_MOD 131>;
1768 resets = <&cpg 131>;
1775 clocks = <&cpg CPG_MOD 128>;
1777 resets = <&cpg 128>;
1784 clocks = <&cpg CPG_MOD 127>;
1786 resets = <&cpg 127>;
1795 clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>,
1796 <&cpg CPG_MOD 722>;
1798 resets = <&cpg 724>;
1829 clocks = <&cpg CPG_MOD 726>;
1831 resets = <&cpg 726>;
1855 clocks = <&cpg CPG_MOD 725>;
1857 resets = <&cpg 725>;
1889 clocks = <&cpg CPG_MOD 124>;
1892 resets = <&cpg 124>;
1908 clocks = <&cpg CPG_MOD 329>;
1911 resets = <&cpg 329>;