Lines Matching +full:0 +full:xf0100000
20 #size-cells = <0>;
21 cpu@0 {
24 reg = <0x0>;
35 reg = <0xc2800000 0x1000>,
36 <0xc2000000 0x1000>;
41 reg = <0xf0100000 0x1000>;
53 reg = <0xfe400000 0x400>;
68 reg = <0xfe910000 0x3000>;
77 reg = <0xfe914000 0x3000>;
87 reg = <0xe6138000 0x170>;
100 reg = <0xe6900000 4>,
101 <0xe6900010 4>,
102 <0xe6900020 1>,
103 <0xe6900040 1>,
104 <0xe6900060 1>;
122 reg = <0xe6900004 4>,
123 <0xe6900014 4>,
124 <0xe6900024 1>,
125 <0xe6900044 1>,
126 <0xe6900064 1>;
144 reg = <0xe6900008 4>,
145 <0xe6900018 4>,
146 <0xe6900028 1>,
147 <0xe6900048 1>,
148 <0xe6900068 1>;
166 reg = <0xe690000c 4>,
167 <0xe690001c 4>,
168 <0xe690002c 1>,
169 <0xe690004c 1>,
170 <0xe690006c 1>;
185 reg = <0xe9a00000 0x800>,
186 <0xe9a01800 0x800>;
192 #size-cells = <0>;
198 #size-cells = <0>;
200 reg = <0xfff20000 0x425>;
212 #size-cells = <0>;
214 reg = <0xe6c20000 0x425>;
226 reg = <0xe6c40000 0x100>;
236 reg = <0xe6c50000 0x100>;
246 reg = <0xe6c60000 0x100>;
256 reg = <0xe6c70000 0x100>;
266 reg = <0xe6c80000 0x100>;
276 reg = <0xe6cb0000 0x100>;
286 reg = <0xe6cc0000 0x100>;
296 reg = <0xe6cd0000 0x100>;
306 reg = <0xe6c30000 0x100>;
316 reg = <0xe6050000 0x8000>,
317 <0xe605800c 0x20>;
320 gpio-ranges = <&pfc 0 0 212>;
322 <&irqpin0 0 0>, <&irqpin0 1 0>, <&irqpin0 2 0>, <&irqpin0 3 0>,
323 <&irqpin0 4 0>, <&irqpin0 5 0>, <&irqpin0 6 0>, <&irqpin0 7 0>,
324 <&irqpin1 0 0>, <&irqpin1 1 0>, <&irqpin1 2 0>, <&irqpin1 3 0>,
325 <&irqpin1 4 0>, <&irqpin1 5 0>, <&irqpin1 6 0>, <&irqpin1 7 0>,
326 <&irqpin2 0 0>, <&irqpin2 1 0>, <&irqpin2 2 0>, <&irqpin2 3 0>,
327 <&irqpin2 4 0>, <&irqpin2 5 0>, <&irqpin2 6 0>, <&irqpin2 7 0>,
328 <&irqpin3 0 0>, <&irqpin3 1 0>, <&irqpin3 2 0>, <&irqpin3 3 0>,
329 <&irqpin3 4 0>, <&irqpin3 5 0>, <&irqpin3 6 0>, <&irqpin3 7 0>;
335 reg = <0xe6600000 0x148>;
344 reg = <0xe6bd0000 0x100>;
354 reg = <0xe6850000 0x100>;
367 reg = <0xe6860000 0x100>;
380 reg = <0xe6870000 0x100>;
394 reg = <0xfe1f0000 0x400>;
395 interrupts = <GIC_SPI 9 0x4>;
403 reg = <0xfe940000 0x4000>;
414 #size-cells = <0>;
416 port@0 {
417 reg = <0>;
427 reg = <0xfe944000 0x4000>;
438 #size-cells = <0>;
440 port@0 {
441 reg = <0>;
458 reg = <0xfff80000 0x2c>;
473 reg = <0xfff90000 0x2c>;
494 #clock-cells = <0>;
499 #clock-cells = <0>;
500 clock-frequency = <0>;
504 #clock-cells = <0>;
505 clock-frequency = <0>;
509 #clock-cells = <0>;
514 #clock-cells = <0>;
515 clock-frequency = <0>;
519 #clock-cells = <0>;
520 clock-frequency = <0>;
524 #clock-cells = <0>;
525 clock-frequency = <0>;
529 #clock-cells = <0>;
530 clock-frequency = <0>;
534 #clock-cells = <0>;
535 clock-frequency = <0>;
539 #clock-cells = <0>;
540 clock-frequency = <0>;
546 reg = <0xe6150000 0x10000>;
560 reg = <0xe6150008 4>;
561 clocks = <&pllc1_div2_clk>, <0>, <&dv_clk>,
563 <&extal1_div2_clk>, <&extalr_clk>, <0>,
564 <0>;
565 #clock-cells = <0>;
569 reg = <0xe615000c 4>;
570 clocks = <&pllc1_div2_clk>, <0>, <&dv_clk>,
572 <&extal1_div2_clk>, <&extalr_clk>, <0>,
573 <0>;
574 #clock-cells = <0>;
578 reg = <0xe6150010 4>;
579 clocks = <&pllc1_div2_clk>, <&fmsick_clk>, <0>, <0>;
580 #clock-cells = <0>;
584 reg = <0xe6150014 4>;
585 clocks = <&pllc1_div2_clk>, <&fmsock_clk>, <0>, <0>;
586 #clock-cells = <0>;
590 reg = <0xe6150018 4>;
591 clocks = <&pllc1_div2_clk>, <&fsiack_clk>, <0>, <0>;
592 #clock-cells = <0>;
596 reg = <0xe6150080 4>;
598 <&cpg_clocks R8A7740_CLK_USB24S>, <0>, <0>;
599 #clock-cells = <0>;
603 reg = <0xe6150084 4>;
605 <&cpg_clocks R8A7740_CLK_USB24S>, <0>, <0>;
606 #clock-cells = <0>;
610 reg = <0xe6150088 4>;
612 <0>;
613 #clock-cells = <0>;
617 reg = <0xe615009c 4>;
619 #clock-cells = <0>;
626 #clock-cells = <0>;
633 #clock-cells = <0>;
641 reg = <0xe6150080 4>;
652 reg = <0xe6150134 4>, <0xe6150038 4>;
670 reg = <0xe6150138 4>, <0xe6150040 4>;
698 reg = <0xe615013c 4>, <0xe6150048 4>;
720 reg = <0xe6150140 4>, <0xe615004c 4>;
737 reg = <0xe6180000 0x8000>, <0xe6188000 0x8000>;
742 #size-cells = <0>;
743 #power-domain-cells = <0>;
747 #power-domain-cells = <0>;
752 #power-domain-cells = <0>;
757 #power-domain-cells = <0>;
763 #size-cells = <0>;
764 #power-domain-cells = <0>;
768 #power-domain-cells = <0>;
775 #size-cells = <0>;
776 #power-domain-cells = <0>;
780 #power-domain-cells = <0>;
785 #power-domain-cells = <0>;
790 #power-domain-cells = <0>;
796 #power-domain-cells = <0>;