Lines Matching +full:0 +full:xe6550000
21 #size-cells = <0>;
23 cpu0: cpu@0 {
26 reg = <0>;
33 L2_CA15: cache-controller-0 {
65 reg = <0 0xe6790000 0 0x10000>;
71 reg = <0 0xe67a0000 0 0x10000>;
77 #size-cells = <0>;
79 reg = <0 0xe60b0000 0 0x428>;
89 reg = <0 0xe6130000 0 0x1004>;
108 reg = <0 0xe61c0000 0 0x200>;
109 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
149 reg = <0 0xe61c0200 0 0x200>;
182 reg = <0 0xe6050000 0 0x9000>;
186 <&pfc 0 0 31>, <&pfc 32 32 9>,
193 <&irqc0 0 0>, <&irqc0 1 0>, <&irqc0 2 0>, <&irqc0 3 0>,
194 <&irqc0 4 0>, <&irqc0 5 0>, <&irqc0 6 0>, <&irqc0 7 0>,
195 <&irqc0 8 0>, <&irqc0 9 0>, <&irqc0 10 0>, <&irqc0 11 0>,
196 <&irqc0 12 0>, <&irqc0 13 0>, <&irqc0 14 0>, <&irqc0 15 0>,
197 <&irqc0 16 0>, <&irqc0 17 0>, <&irqc0 18 0>, <&irqc0 19 0>,
198 <&irqc0 20 0>, <&irqc0 21 0>, <&irqc0 22 0>, <&irqc0 23 0>,
199 <&irqc0 24 0>, <&irqc0 25 0>, <&irqc0 26 0>, <&irqc0 27 0>,
200 <&irqc0 28 0>, <&irqc0 29 0>, <&irqc0 30 0>, <&irqc0 31 0>,
201 <&irqc1 0 0>, <&irqc1 1 0>, <&irqc1 2 0>, <&irqc1 3 0>,
202 <&irqc1 4 0>, <&irqc1 5 0>, <&irqc1 6 0>, <&irqc1 7 0>,
203 <&irqc1 8 0>, <&irqc1 9 0>, <&irqc1 10 0>, <&irqc1 11 0>,
204 <&irqc1 12 0>, <&irqc1 13 0>, <&irqc1 14 0>, <&irqc1 15 0>,
205 <&irqc1 16 0>, <&irqc1 17 0>, <&irqc1 18 0>, <&irqc1 19 0>,
206 <&irqc1 20 0>, <&irqc1 21 0>, <&irqc1 22 0>, <&irqc1 23 0>,
207 <&irqc1 24 0>, <&irqc1 25 0>;
213 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>,
214 <0 0xe61f0200 0 0x38>, <0 0xe61f0300 0 0x38>;
222 #size-cells = <0>;
224 reg = <0 0xe6500000 0 0x428>;
233 #size-cells = <0>;
235 reg = <0 0xe6510000 0 0x428>;
244 #size-cells = <0>;
246 reg = <0 0xe6520000 0 0x428>;
255 #size-cells = <0>;
257 reg = <0 0xe6530000 0 0x428>;
266 #size-cells = <0>;
268 reg = <0 0xe6540000 0 0x428>;
277 #size-cells = <0>;
279 reg = <0 0xe6550000 0 0x428>;
288 #size-cells = <0>;
290 reg = <0 0xe6560000 0 0x428>;
299 #size-cells = <0>;
301 reg = <0 0xe6570000 0 0x428>;
310 reg = <0 0xe6c20000 0 0x100>;
320 reg = <0 0xe6c30000 0 0x100>;
330 reg = <0 0xe6c40000 0 0x100>;
340 reg = <0 0xe6c50000 0 0x100>;
350 reg = <0 0xe6ce0000 0 0x100>;
360 reg = <0 0xe6cf0000 0 0x100>;
370 reg = <0 0xee100000 0 0x100>;
380 reg = <0 0xee120000 0 0x100>;
390 reg = <0 0xee140000 0 0x100>;
400 reg = <0 0xee200000 0 0x80>;
410 reg = <0 0xee220000 0 0x80>;
421 #address-cells = <0>;
423 reg = <0 0xf1001000 0 0x1000>,
424 <0 0xf1002000 0 0x2000>,
425 <0 0xf1004000 0 0x2000>,
426 <0 0xf1006000 0 0x2000>;
438 ranges = <0 0 0 0x20000000>;
439 reg = <0 0xfec10000 0 0x400>;
452 #clock-cells = <0>;
457 #clock-cells = <0>;
462 #clock-cells = <0>;
467 #clock-cells = <0>;
469 clock-frequency = <0>;
473 #clock-cells = <0>;
475 clock-frequency = <0>;
481 reg = <0 0xe6150000 0 0x10000>;
493 reg = <0 0xe6150010 0 4>;
494 clocks = <&pll1_div2_clk>, <0>,
495 <&cpg_clocks R8A73A4_CLK_PLL2S>, <0>;
496 #clock-cells = <0>;
501 reg = <0 0xe6150074 0 4>;
503 <0>, <&extal2_clk>;
504 #clock-cells = <0>;
508 reg = <0 0xe6150078 0 4>;
510 <0>, <&extal2_clk>;
511 #clock-cells = <0>;
515 reg = <0 0xe615007c 0 4>;
517 <0>, <&extal2_clk>;
518 #clock-cells = <0>;
522 reg = <0 0xe6150240 0 4>;
524 <0>, <&extal2_clk>;
525 #clock-cells = <0>;
529 reg = <0 0xe6150244 0 4>;
531 <0>, <&extal2_clk>;
532 #clock-cells = <0>;
536 reg = <0 0xe6150008 0 4>;
538 <0>, <&extal2_clk>, <&main_div2_clk>,
539 <&extalr_clk>, <0>, <0>;
540 #clock-cells = <0>;
544 reg = <0 0xe615000c 0 4>;
546 <0>, <&extal2_clk>, <&main_div2_clk>,
547 <&extalr_clk>, <0>, <0>;
548 #clock-cells = <0>;
552 reg = <0 0xe615001c 0 4>;
554 <0>, <&extal2_clk>, <&main_div2_clk>,
555 <&extalr_clk>, <0>, <0>;
556 #clock-cells = <0>;
560 reg = <0 0xe6150014 0 4>;
562 <0>, <&extal2_clk>, <&main_div2_clk>,
563 <&extalr_clk>, <0>, <0>;
564 #clock-cells = <0>;
568 reg = <0 0xe6150034 0 4>;
570 <0>, <&extal2_clk>, <&main_div2_clk>,
571 <&extalr_clk>, <0>, <0>;
572 #clock-cells = <0>;
576 reg = <0 0xe6150018 0 4>;
578 <&fsiack_clk>, <0>;
579 #clock-cells = <0>;
583 reg = <0 0xe6150090 0 4>;
585 <&fsibck_clk>, <0>;
586 #clock-cells = <0>;
590 reg = <0 0xe6150080 0 4>;
593 #clock-cells = <0>;
597 reg = <0 0xe6150098 0 4>;
599 #clock-cells = <0>;
603 reg = <0 0xe615026c 0 4>;
605 <&cpg_clocks R8A73A4_CLK_PLL2S>, <0>;
606 #clock-cells = <0>;
610 reg = <0 0xe6150094 0 4>;
613 #clock-cells = <0>;
620 #clock-cells = <0>;
627 #clock-cells = <0>;
634 #clock-cells = <0>;
641 #clock-cells = <0>;
649 reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
665 reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
688 reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
704 reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
717 reg = <0 0xff000044 0 4>;
722 reg = <0 0xe6180000 0 0x8000>, <0 0xe6188000 0 0x8000>;
727 #size-cells = <0>;
728 #power-domain-cells = <0>;
730 pd_c4: c4@0 {
731 reg = <0>;
733 #size-cells = <0>;
734 #power-domain-cells = <0>;
738 #power-domain-cells = <0>;
743 #power-domain-cells = <0>;
749 #size-cells = <0>;
750 #power-domain-cells = <0>;
754 #power-domain-cells = <0>;
761 #size-cells = <0>;
762 #power-domain-cells = <0>;
766 #power-domain-cells = <0>;
773 #size-cells = <0>;
774 #power-domain-cells = <0>;
778 #power-domain-cells = <0>;
785 #power-domain-cells = <0>;
790 #power-domain-cells = <0>;
795 #power-domain-cells = <0>;
801 #size-cells = <0>;
802 #power-domain-cells = <0>;
806 #power-domain-cells = <0>;
812 #power-domain-cells = <0>;
817 #power-domain-cells = <0>;
823 #size-cells = <0>;
824 #power-domain-cells = <0>;
828 #power-domain-cells = <0>;
833 #power-domain-cells = <0>;
839 #power-domain-cells = <0>;
845 #size-cells = <0>;
846 #power-domain-cells = <0>;
850 #power-domain-cells = <0>;
855 #power-domain-cells = <0>;