Lines Matching +full:0 +full:xfcfee000
32 #clock-cells = <0>;
43 ranges = <0 0 0x18000000>;
48 #size-cells = <0>;
50 cpu@0 {
53 reg = <0>;
62 #clock-cells = <0>;
65 clock-frequency = <0>;
69 #clock-cells = <0>;
77 #clock-cells = <0>;
86 interrupts-extended = <&gic GIC_PPI 0 IRQ_TYPE_LEVEL_HIGH>;
90 #clock-cells = <0>;
93 clock-frequency = <0>;
97 #clock-cells = <0>;
100 clock-frequency = <0>;
113 reg = <0x3ffff000 0x1000>;
123 reg = <0xe8007000 64>;
136 reg = <0xe8007800 64>;
149 reg = <0xe8008000 64>;
162 reg = <0xe8008800 64>;
175 reg = <0xe8009000 64>;
188 reg = <0xe8009800 64>;
201 reg = <0xe800a000 64>;
214 reg = <0xe800a800 64>;
227 reg = <0xe800c800 0x24>;
236 #size-cells = <0>;
242 reg = <0xe800d000 0x24>;
251 #size-cells = <0>;
257 reg = <0xe800d800 0x24>;
266 #size-cells = <0>;
272 reg = <0xe800e000 0x24>;
281 #size-cells = <0>;
287 reg = <0xe800e800 0x24>;
296 #size-cells = <0>;
302 reg = <0xe8010000 0x1a0>;
312 reg = <0xe8207000 0x1a0>;
322 reg = <0xe804c800 0x80>;
335 reg = <0xe804e000 0x100>;
351 reg = <0xe804e800 0x100>;
368 #address-cells = <0>;
370 reg = <0xe8201000 0x1000>,
371 <0xe8202000 0x1000>;
376 reg = <0xe8203000 0x800>,
377 <0xe8204800 0x200>;
383 #size-cells = <0>;
388 reg = <0xe8210000 0x3000>;
398 reg = <0xfcfe0000 0x6>;
408 reg = <0xfcfe0000 0x18>;
411 #power-domain-cells = <0>;
418 reg = <0xfcfe0420 4>;
427 reg = <0xfcfe0424 4>;
440 reg = <0xfcfe0428 4>;
449 reg = <0xfcfe042c 4>;
458 reg = <0xfcfe0430 4>;
467 reg = <0xfcfe0434 4>;
476 reg = <0xfcfe0438 4>;
488 reg = <0xfcfe043c 4>;
500 reg = <0xfcfe0444 4>;
512 reg = <0xfcfe3000 0x4230>;
514 port0: gpio-0 {
517 gpio-ranges = <&pinctrl 0 0 6>;
523 gpio-ranges = <&pinctrl 0 16 16>;
529 gpio-ranges = <&pinctrl 0 32 16>;
535 gpio-ranges = <&pinctrl 0 48 16>;
541 gpio-ranges = <&pinctrl 0 64 16>;
547 gpio-ranges = <&pinctrl 0 80 11>;
553 gpio-ranges = <&pinctrl 0 96 16>;
559 gpio-ranges = <&pinctrl 0 112 16>;
565 gpio-ranges = <&pinctrl 0 128 16>;
571 gpio-ranges = <&pinctrl 0 144 8>;
577 gpio-ranges = <&pinctrl 0 160 16>;
583 gpio-ranges = <&pinctrl 0 176 16>;
589 reg = <0xfcfec000 0x30>;
598 reg = <0xfcfec400 0x30>;
607 #size-cells = <0>;
609 reg = <0xfcfee000 0x44>;
628 #size-cells = <0>;
630 reg = <0xfcfee400 0x44>;
649 #size-cells = <0>;
651 reg = <0xfcfee800 0x44>;
670 #size-cells = <0>;
672 reg = <0xfcfeec00 0x44>;
693 #address-cells = <0>;
695 reg = <0xfcfef800 0x6>;
697 <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
698 <1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
699 <2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
700 <3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
701 <4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
702 <5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
703 <6 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
704 <7 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
705 interrupt-map-mask = <7 0>;
710 reg = <0xfcff0000 0x400>;
721 reg = <0xfcff1000 0x2e>;
735 #clock-cells = <0>;
738 clock-frequency = <0>;