Lines Matching +full:dsi +full:- +full:rx
1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/interconnect/qcom,msm8974.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/clock/qcom,gcc-msm8974.h>
7 #include <dt-bindings/clock/qcom,mmcc-msm8974.h>
8 #include <dt-bindings/clock/qcom,rpmcc.h>
9 #include <dt-bindings/reset/qcom,gcc-msm8974.h>
10 #include <dt-bindings/gpio/gpio.h>
13 #address-cells = <1>;
14 #size-cells = <1>;
15 interrupt-parent = <&intc>;
19 compatible = "fixed-clock";
20 #clock-cells = <0>;
21 clock-frequency = <19200000>;
25 compatible = "fixed-clock";
26 #clock-cells = <0>;
27 clock-frequency = <32768>;
32 #address-cells = <1>;
33 #size-cells = <0>;
38 enable-method = "qcom,kpss-acc-v2";
41 next-level-cache = <&L2>;
44 cpu-idle-states = <&CPU_SPC>;
49 enable-method = "qcom,kpss-acc-v2";
52 next-level-cache = <&L2>;
55 cpu-idle-states = <&CPU_SPC>;
60 enable-method = "qcom,kpss-acc-v2";
63 next-level-cache = <&L2>;
66 cpu-idle-states = <&CPU_SPC>;
71 enable-method = "qcom,kpss-acc-v2";
74 next-level-cache = <&L2>;
77 cpu-idle-states = <&CPU_SPC>;
80 L2: l2-cache {
82 cache-level = <2>;
83 cache-unified;
87 idle-states {
89 compatible = "qcom,idle-state-spc",
90 "arm,idle-state";
91 entry-latency-us = <150>;
92 exit-latency-us = <200>;
93 min-residency-us = <2000>;
100 compatible = "qcom,scm-msm8974", "qcom,scm";
102 clock-names = "core", "bus", "iface";
112 compatible = "qcom,krait-pmu";
117 compatible = "qcom,msm8974-rpm-proc", "qcom,rpm-proc";
119 master-stats {
120 compatible = "qcom,rpm-master-stats";
121 qcom,rpm-msg-ram = <&apss_master_stats>,
125 qcom,master-names = "APSS",
131 smd-edge {
134 qcom,smd-edge = <15>;
136 rpm_requests: rpm-requests {
137 compatible = "qcom,rpm-msm8974";
138 qcom,smd-channels = "rpm_requests";
140 rpmcc: clock-controller {
141 compatible = "qcom,rpmcc-msm8974", "qcom,rpmcc";
142 #clock-cells = <1>;
144 clock-names = "xo";
150 reserved-memory {
151 #address-cells = <1>;
152 #size-cells = <1>;
157 no-map;
162 no-map;
167 no-map;
172 no-map;
177 no-map;
182 no-map;
187 no-map;
192 no-map;
196 compatible = "qcom,rmtfs-mem";
198 no-map;
200 qcom,client-id = <1>;
207 memory-region = <&smem_region>;
208 qcom,rpm-msg-ram = <&rpm_msg_ram>;
213 smp2p-adsp {
217 interrupt-parent = <&intc>;
222 qcom,local-pid = <0>;
223 qcom,remote-pid = <2>;
225 adsp_smp2p_out: master-kernel {
226 qcom,entry-name = "master-kernel";
227 #qcom,smem-state-cells = <1>;
230 adsp_smp2p_in: slave-kernel {
231 qcom,entry-name = "slave-kernel";
233 interrupt-controller;
234 #interrupt-cells = <2>;
238 smp2p-modem {
242 interrupt-parent = <&intc>;
247 qcom,local-pid = <0>;
248 qcom,remote-pid = <1>;
250 modem_smp2p_out: master-kernel {
251 qcom,entry-name = "master-kernel";
252 #qcom,smem-state-cells = <1>;
255 modem_smp2p_in: slave-kernel {
256 qcom,entry-name = "slave-kernel";
258 interrupt-controller;
259 #interrupt-cells = <2>;
263 smp2p-wcnss {
267 interrupt-parent = <&intc>;
272 qcom,local-pid = <0>;
273 qcom,remote-pid = <4>;
275 wcnss_smp2p_out: master-kernel {
276 qcom,entry-name = "master-kernel";
278 #qcom,smem-state-cells = <1>;
281 wcnss_smp2p_in: slave-kernel {
282 qcom,entry-name = "slave-kernel";
284 interrupt-controller;
285 #interrupt-cells = <2>;
292 #address-cells = <1>;
293 #size-cells = <0>;
295 qcom,ipc-1 = <&apcs 8 13>;
296 qcom,ipc-2 = <&apcs 8 9>;
297 qcom,ipc-3 = <&apcs 8 19>;
302 #qcom,smem-state-cells = <1>;
309 interrupt-controller;
310 #interrupt-cells = <2>;
317 interrupt-controller;
318 #interrupt-cells = <2>;
325 interrupt-controller;
326 #interrupt-cells = <2>;
331 #address-cells = <1>;
332 #size-cells = <1>;
334 compatible = "simple-bus";
336 intc: interrupt-controller@f9000000 {
337 compatible = "qcom,msm-qgic2";
338 interrupt-controller;
339 #interrupt-cells = <3>;
349 saw_l2: power-controller@f9012000 {
356 compatible = "qcom,apss-wdt-msm8974", "qcom,kpss-wdt";
364 #address-cells = <1>;
365 #size-cells = <1>;
367 compatible = "arm,armv7-timer-mem";
369 clock-frequency = <19200000>;
372 frame-number = <0>;
380 frame-number = <1>;
387 frame-number = <2>;
394 frame-number = <3>;
401 frame-number = <4>;
408 frame-number = <5>;
415 frame-number = <6>;
422 acc0: power-manager@f9088000 {
423 compatible = "qcom,kpss-acc-v2";
427 saw0: power-controller@f9089000 {
428 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
432 acc1: power-manager@f9098000 {
433 compatible = "qcom,kpss-acc-v2";
437 saw1: power-controller@f9099000 {
438 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
442 acc2: power-manager@f90a8000 {
443 compatible = "qcom,kpss-acc-v2";
447 saw2: power-controller@f90a9000 {
448 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
452 acc3: power-manager@f90b8000 {
453 compatible = "qcom,kpss-acc-v2";
457 saw3: power-controller@f90b9000 {
458 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
463 compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4";
465 reg-names = "hc", "core";
468 interrupt-names = "hc_irq", "pwr_irq";
472 clock-names = "iface", "core", "xo";
473 bus-width = <8>;
474 non-removable;
480 compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4";
482 reg-names = "hc", "core";
485 interrupt-names = "hc_irq", "pwr_irq";
489 clock-names = "iface", "core", "xo";
490 bus-width = <4>;
492 #address-cells = <1>;
493 #size-cells = <0>;
499 compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4";
501 reg-names = "hc", "core";
504 interrupt-names = "hc_irq", "pwr_irq";
508 clock-names = "iface", "core", "xo";
509 bus-width = <4>;
511 #address-cells = <1>;
512 #size-cells = <0>;
518 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
522 clock-names = "core", "iface";
527 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
531 clock-names = "core", "iface";
532 pinctrl-names = "default";
533 pinctrl-0 = <&blsp1_uart2_default>;
539 compatible = "qcom,i2c-qup-v2.1.1";
543 clock-names = "core", "iface";
544 pinctrl-names = "default", "sleep";
545 pinctrl-0 = <&blsp1_i2c1_default>;
546 pinctrl-1 = <&blsp1_i2c1_sleep>;
547 #address-cells = <1>;
548 #size-cells = <0>;
553 compatible = "qcom,i2c-qup-v2.1.1";
557 clock-names = "core", "iface";
558 pinctrl-names = "default", "sleep";
559 pinctrl-0 = <&blsp1_i2c2_default>;
560 pinctrl-1 = <&blsp1_i2c2_sleep>;
561 #address-cells = <1>;
562 #size-cells = <0>;
567 compatible = "qcom,i2c-qup-v2.1.1";
571 clock-names = "core", "iface";
572 pinctrl-names = "default", "sleep";
573 pinctrl-0 = <&blsp1_i2c3_default>;
574 pinctrl-1 = <&blsp1_i2c3_sleep>;
575 #address-cells = <1>;
576 #size-cells = <0>;
581 compatible = "qcom,i2c-qup-v2.1.1";
585 clock-names = "core", "iface";
586 pinctrl-names = "default", "sleep";
587 pinctrl-0 = <&blsp1_i2c6_default>;
588 pinctrl-1 = <&blsp1_i2c6_sleep>;
589 #address-cells = <1>;
590 #size-cells = <0>;
593 blsp2_dma: dma-controller@f9944000 {
594 compatible = "qcom,bam-v1.4.0";
598 clock-names = "bam_clk";
599 #dma-cells = <1>;
604 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
608 clock-names = "core", "iface";
609 pinctrl-names = "default", "sleep";
610 pinctrl-0 = <&blsp2_uart1_default>;
611 pinctrl-1 = <&blsp2_uart1_sleep>;
616 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
620 clock-names = "core", "iface";
625 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
629 clock-names = "core", "iface";
630 pinctrl-names = "default";
631 pinctrl-0 = <&blsp2_uart4_default>;
637 compatible = "qcom,i2c-qup-v2.1.1";
641 clock-names = "core", "iface";
642 pinctrl-names = "default", "sleep";
643 pinctrl-0 = <&blsp2_i2c2_default>;
644 pinctrl-1 = <&blsp2_i2c2_sleep>;
645 #address-cells = <1>;
646 #size-cells = <0>;
651 compatible = "qcom,i2c-qup-v2.1.1";
655 clock-names = "core", "iface";
657 dma-names = "tx", "rx";
658 pinctrl-names = "default", "sleep";
659 pinctrl-0 = <&blsp2_i2c5_default>;
660 pinctrl-1 = <&blsp2_i2c5_sleep>;
661 #address-cells = <1>;
662 #size-cells = <0>;
667 compatible = "qcom,i2c-qup-v2.1.1";
671 clock-names = "core", "iface";
672 pinctrl-names = "default", "sleep";
673 pinctrl-0 = <&blsp2_i2c6_default>;
674 pinctrl-1 = <&blsp2_i2c6_sleep>;
675 #address-cells = <1>;
676 #size-cells = <0>;
680 compatible = "qcom,ci-hdrc";
686 clock-names = "iface", "core";
687 assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>;
688 assigned-clock-rates = <75000000>;
690 reset-names = "core";
693 ahb-burst-config = <0>;
694 phy-names = "usb-phy";
696 #reset-cells = <1>;
699 usb_hs1_phy: phy-0 {
700 compatible = "qcom,usb-hs-phy-msm8974",
701 "qcom,usb-hs-phy";
702 #phy-cells = <0>;
704 clock-names = "ref", "sleep";
706 reset-names = "phy", "por";
710 usb_hs2_phy: phy-1 {
711 compatible = "qcom,usb-hs-phy-msm8974",
712 "qcom,usb-hs-phy";
713 #phy-cells = <0>;
715 clock-names = "ref", "sleep";
717 reset-names = "phy", "por";
727 clock-names = "core";
731 compatible = "qcom,pronto-v2-pil", "qcom,pronto";
733 reg-names = "ccu", "dxe", "pmu";
735 memory-region = <&wcnss_region>;
737 interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>,
742 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
744 qcom,smem-states = <&wcnss_smp2p_out 0>;
745 qcom,smem-state-names = "stop";
753 clock-names = "xo";
756 smd-edge {
760 qcom,smd-edge = <6>;
764 qcom,smd-channels = "WCNSS_CTRL";
770 compatible = "qcom,wcnss-bt";
774 compatible = "qcom,wcnss-wlan";
778 interrupt-names = "tx", "rx";
780 qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>;
781 qcom,smem-state-names = "tx-enable",
782 "tx-rings-empty";
789 compatible = "qcom,msm8974-rpm-stats";
794 compatible = "arm,coresight-tmc", "arm,primecell";
798 clock-names = "apb_pclk", "atclk";
800 out-ports {
803 remote-endpoint = <&replicator_in>;
808 in-ports {
811 remote-endpoint = <&merger_out>;
818 compatible = "arm,coresight-tpiu", "arm,primecell";
822 clock-names = "apb_pclk", "atclk";
824 in-ports {
827 remote-endpoint = <&replicator_out1>;
834 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
838 clock-names = "apb_pclk", "atclk";
840 in-ports {
841 #address-cells = <1>;
842 #size-cells = <0>;
846 * 0 - not-connected
847 * 1 - connected trought funnel to Multimedia CPU
848 * 2 - connected to Wireless CPU
849 * 3 - not-connected
850 * 4 - not-connected
851 * 6 - not-connected
852 * 7 - connected to STM
857 remote-endpoint = <&kpss_out>;
862 out-ports {
865 remote-endpoint = <&merger_in1>;
872 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
876 clock-names = "apb_pclk", "atclk";
878 in-ports {
879 #address-cells = <1>;
880 #size-cells = <0>;
884 * 0 - connected trought funnel to Audio, Modem and
886 * 2...7 - not-connected
891 remote-endpoint = <&funnel1_out>;
896 out-ports {
899 remote-endpoint = <&etf_in>;
906 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
910 clock-names = "apb_pclk", "atclk";
912 out-ports {
913 #address-cells = <1>;
914 #size-cells = <0>;
919 remote-endpoint = <&etr_in>;
925 remote-endpoint = <&tpiu_in>;
930 in-ports {
933 remote-endpoint = <&etf_out>;
940 compatible = "arm,coresight-tmc", "arm,primecell";
944 clock-names = "apb_pclk", "atclk";
946 in-ports {
949 remote-endpoint = <&replicator_out0>;
956 compatible = "arm,coresight-etm4x", "arm,primecell";
960 clock-names = "apb_pclk", "atclk";
964 out-ports {
967 remote-endpoint = <&kpss_in0>;
974 compatible = "arm,coresight-etm4x", "arm,primecell";
978 clock-names = "apb_pclk", "atclk";
982 out-ports {
985 remote-endpoint = <&kpss_in1>;
992 compatible = "arm,coresight-etm4x", "arm,primecell";
996 clock-names = "apb_pclk", "atclk";
1000 out-ports {
1003 remote-endpoint = <&kpss_in2>;
1010 compatible = "arm,coresight-etm4x", "arm,primecell";
1014 clock-names = "apb_pclk", "atclk";
1018 out-ports {
1021 remote-endpoint = <&kpss_in3>;
1029 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1033 clock-names = "apb_pclk", "atclk";
1035 in-ports {
1036 #address-cells = <1>;
1037 #size-cells = <0>;
1042 remote-endpoint = <&etm0_out>;
1048 remote-endpoint = <&etm1_out>;
1054 remote-endpoint = <&etm2_out>;
1060 remote-endpoint = <&etm3_out>;
1065 out-ports {
1068 remote-endpoint = <&funnel1_in5>;
1076 compatible = "qcom,msm8974-bimc";
1077 #interconnect-cells = <1>;
1078 clock-names = "bus", "bus_a";
1083 gcc: clock-controller@fc400000 {
1084 compatible = "qcom,gcc-msm8974";
1085 #clock-cells = <1>;
1086 #reset-cells = <1>;
1087 #power-domain-cells = <1>;
1092 clock-names = "xo",
1097 compatible = "qcom,rpm-msg-ram";
1100 #address-cells = <1>;
1101 #size-cells = <1>;
1123 compatible = "qcom,msm8974-snoc";
1124 #interconnect-cells = <1>;
1125 clock-names = "bus", "bus_a";
1132 compatible = "qcom,msm8974-pnoc";
1133 #interconnect-cells = <1>;
1134 clock-names = "bus", "bus_a";
1141 compatible = "qcom,msm8974-ocmemnoc";
1142 #interconnect-cells = <1>;
1143 clock-names = "bus", "bus_a";
1150 compatible = "qcom,msm8974-mmssnoc";
1151 #interconnect-cells = <1>;
1152 clock-names = "bus", "bus_a";
1159 compatible = "qcom,msm8974-cnoc";
1160 #interconnect-cells = <1>;
1161 clock-names = "bus", "bus_a";
1166 tsens: thermal-sensor@fc4a9000 {
1167 compatible = "qcom,msm8974-tsens", "qcom,tsens-v0_1";
1170 nvmem-cells = <&tsens_mode>,
1197 nvmem-cell-names = "mode",
1226 interrupt-names = "uplow";
1227 #thermal-sensor-cells = <1>;
1236 compatible = "qcom,msm8974-qfprom", "qcom,qfprom";
1238 #address-cells = <1>;
1239 #size-cells = <1>;
1246 tsens_s0_p1: s0-p1@d1 {
1251 tsens_s1_p1: s1-p1@d2 {
1256 tsens_s2_p1: s2-p1@d2 {
1261 tsens_s3_p1: s3-p1@d3 {
1266 tsens_s4_p1: s4-p1@d4 {
1271 tsens_s5_p1: s5-p1@d4 {
1276 tsens_s6_p1: s6-p1@d5 {
1281 tsens_s7_p1: s7-p1@d6 {
1286 tsens_s8_p1: s8-p1@d7 {
1296 tsens_s9_p1: s9-p1@d8 {
1311 tsens_s0_p2: s0-p2@da {
1316 tsens_s1_p2: s1-p2@db {
1321 tsens_s2_p2: s2-p2@dc {
1326 tsens_s3_p2: s3-p2@dc {
1331 tsens_s4_p2: s4-p2@dd {
1336 tsens_s5_p2: s5-p2@de {
1341 tsens_s6_p2: s6-p2@df {
1346 tsens_s7_p2: s7-p2@e0 {
1351 tsens_s8_p2: s8-p2@e0 {
1356 tsens_s9_p2: s9-p2@e1 {
1366 tsens_s5_p2_backup: s5-p2_backup@e3 {
1376 tsens_s6_p2_backup: s6-p2_backup@e4 {
1381 tsens_s7_p2_backup: s7-p2_backup@e4 {
1386 tsens_s8_p2_backup: s8-p2_backup@e5 {
1391 tsens_s9_p2_backup: s9-p2_backup@e6 {
1406 tsens_s0_p1_backup: s0-p1_backup@441 {
1411 tsens_s1_p1_backup: s1-p1_backup@442 {
1416 tsens_s2_p1_backup: s2-p1_backup@442 {
1421 tsens_s3_p1_backup: s3-p1_backup@443 {
1426 tsens_s4_p1_backup: s4-p1_backup@444 {
1431 tsens_s5_p1_backup: s5-p1_backup@444 {
1436 tsens_s6_p1_backup: s6-p1_backup@445 {
1441 tsens_s7_p1_backup: s7-p1_backup@446 {
1451 tsens_s8_p1_backup: s8-p1_backup@448 {
1456 tsens_s9_p1_backup: s9-p1_backup@448 {
1471 tsens_s0_p2_backup: s0-p2_backup@44b {
1476 tsens_s1_p2_backup: s1-p2_backup@44c {
1481 tsens_s2_p2_backup: s2-p2_backup@44c {
1486 tsens_s3_p2_backup: s3-p2_backup@44d {
1491 tsens_s4_p2_backup: s4-p2_backup@44e {
1498 compatible = "qcom,spmi-pmic-arb";
1499 reg-names = "core", "intr", "cnfg";
1503 interrupt-names = "periph_irq";
1507 #address-cells = <2>;
1508 #size-cells = <0>;
1509 interrupt-controller;
1510 #interrupt-cells = <4>;
1513 bam_dmux_dma: dma-controller@fc834000 {
1514 compatible = "qcom,bam-v1.4.0";
1517 #dma-cells = <1>;
1520 num-channels = <6>;
1521 qcom,num-ees = <1>;
1522 qcom,powered-remotely;
1526 compatible = "qcom,msm8974-mss-pil";
1528 reg-names = "qdsp6", "rmb";
1530 interrupts-extended = <&intc GIC_SPI 24 IRQ_TYPE_EDGE_RISING>,
1535 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
1541 clock-names = "iface", "bus", "mem", "xo";
1544 reset-names = "mss_restart";
1546 qcom,halt-regs = <&tcsr_mutex 0x1180 0x1200 0x1280>;
1548 qcom,smem-states = <&modem_smp2p_out 0>;
1549 qcom,smem-state-names = "stop";
1554 memory-region = <&mba_region>;
1558 memory-region = <&mpss_region>;
1561 bam_dmux: bam-dmux {
1562 compatible = "qcom,bam-dmux";
1564 interrupt-parent = <&modem_smsm>;
1566 interrupt-names = "pc", "pc-ack";
1568 qcom,smem-states = <&apps_smsm 1>, <&apps_smsm 11>;
1569 qcom,smem-state-names = "pc", "pc-ack";
1572 dma-names = "tx", "rx";
1575 smd-edge {
1579 qcom,smd-edge = <0>;
1586 compatible = "qcom,msm8974-tcsr-mutex", "qcom,tcsr-mutex", "syscon";
1588 #hwlock-cells = <1>;
1592 compatible = "qcom,tcsr-msm8974", "syscon";
1597 compatible = "qcom,msm8974-pinctrl";
1599 gpio-controller;
1600 gpio-ranges = <&tlmm 0 0 146>;
1601 #gpio-cells = <2>;
1602 interrupt-controller;
1603 #interrupt-cells = <2>;
1606 sdc1_off: sdc1-off-state {
1607 clk-pins {
1609 bias-disable;
1610 drive-strength = <2>;
1613 cmd-pins {
1615 bias-pull-up;
1616 drive-strength = <2>;
1619 data-pins {
1621 bias-pull-up;
1622 drive-strength = <2>;
1626 sdc2_off: sdc2-off-state {
1627 clk-pins {
1629 bias-disable;
1630 drive-strength = <2>;
1633 cmd-pins {
1635 bias-pull-up;
1636 drive-strength = <2>;
1639 data-pins {
1641 bias-pull-up;
1642 drive-strength = <2>;
1646 blsp1_uart2_default: blsp1-uart2-default-state {
1647 rx-pins {
1650 drive-strength = <2>;
1651 bias-pull-up;
1654 tx-pins {
1657 drive-strength = <4>;
1658 bias-disable;
1662 blsp2_uart1_default: blsp2-uart1-default-state {
1663 tx-rts-pins {
1666 drive-strength = <2>;
1667 bias-disable;
1670 rx-cts-pins {
1673 drive-strength = <2>;
1674 bias-pull-up;
1678 blsp2_uart1_sleep: blsp2-uart1-sleep-state {
1681 drive-strength = <2>;
1682 bias-pull-down;
1685 blsp2_uart4_default: blsp2-uart4-default-state {
1686 tx-rts-pins {
1689 drive-strength = <2>;
1690 bias-disable;
1693 rx-cts-pins {
1696 drive-strength = <2>;
1697 bias-pull-up;
1701 blsp1_i2c1_default: blsp1-i2c1-default-state {
1704 drive-strength = <2>;
1705 bias-disable;
1708 blsp1_i2c1_sleep: blsp1-i2c1-sleep-state {
1711 drive-strength = <2>;
1712 bias-pull-up;
1715 blsp1_i2c2_default: blsp1-i2c2-default-state {
1718 drive-strength = <2>;
1719 bias-disable;
1722 blsp1_i2c2_sleep: blsp1-i2c2-sleep-state {
1725 drive-strength = <2>;
1726 bias-pull-up;
1729 blsp1_i2c3_default: blsp1-i2c3-default-state {
1732 drive-strength = <2>;
1733 bias-disable;
1736 blsp1_i2c3_sleep: blsp1-i2c3-sleep-state {
1739 drive-strength = <2>;
1740 bias-pull-up;
1747 blsp1_i2c6_default: blsp1-i2c6-default-state {
1750 drive-strength = <2>;
1751 bias-disable;
1754 blsp1_i2c6_sleep: blsp1-i2c6-sleep-state {
1757 drive-strength = <2>;
1758 bias-pull-up;
1764 blsp2_i2c2_default: blsp2-i2c2-default-state {
1767 drive-strength = <2>;
1768 bias-disable;
1771 blsp2_i2c2_sleep: blsp2-i2c2-sleep-state {
1774 drive-strength = <2>;
1775 bias-pull-up;
1782 blsp2_i2c5_default: blsp2-i2c5-default-state {
1785 drive-strength = <2>;
1786 bias-disable;
1789 blsp2_i2c5_sleep: blsp2-i2c5-sleep-state {
1792 drive-strength = <2>;
1793 bias-pull-up;
1796 blsp2_i2c6_default: blsp2-i2c6-default-state {
1799 drive-strength = <2>;
1800 bias-disable;
1803 blsp2_i2c6_sleep: blsp2-i2c6-sleep-state {
1806 drive-strength = <2>;
1807 bias-pull-up;
1810 cci_default: cci-default-state {
1811 cci_i2c0_default: cci-i2c0-default-pins {
1814 drive-strength = <2>;
1815 bias-disable;
1818 cci_i2c1_default: cci-i2c1-default-pins {
1821 drive-strength = <2>;
1822 bias-disable;
1826 cci_sleep: cci-sleep-state {
1827 cci_i2c0_sleep: cci-i2c0-sleep-pins {
1830 drive-strength = <2>;
1831 bias-disable;
1834 cci_i2c1_sleep: cci-i2c1-sleep-pins {
1837 drive-strength = <2>;
1838 bias-disable;
1842 spi8_default: spi8_default-state {
1843 mosi-pins {
1847 miso-pins {
1851 cs-pins {
1855 clk-pins {
1862 mmcc: clock-controller@fd8c0000 {
1863 compatible = "qcom,mmcc-msm8974";
1864 #clock-cells = <1>;
1865 #reset-cells = <1>;
1866 #power-domain-cells = <1>;
1880 clock-names = "xo",
1894 mdss: display-subsystem@fd900000 {
1897 reg-names = "mdss_phys", "vbif_phys";
1899 power-domains = <&mmcc MDSS_GDSC>;
1904 clock-names = "iface", "bus", "vsync";
1908 interrupt-controller;
1909 #interrupt-cells = <1>;
1913 #address-cells = <1>;
1914 #size-cells = <1>;
1917 mdp: display-controller@fd900000 {
1918 compatible = "qcom,msm8974-mdp5", "qcom,mdp5";
1920 reg-names = "mdp_phys";
1922 interrupt-parent = <&mdss>;
1929 clock-names = "iface", "bus", "core", "vsync";
1932 interconnect-names = "mdp0-mem";
1935 #address-cells = <1>;
1936 #size-cells = <0>;
1941 remote-endpoint = <&mdss_dsi0_in>;
1948 remote-endpoint = <&mdss_dsi1_in>;
1954 mdss_dsi0: dsi@fd922800 {
1955 compatible = "qcom,msm8974-dsi-ctrl",
1956 "qcom,mdss-dsi-ctrl";
1958 reg-names = "dsi_ctrl";
1960 interrupt-parent = <&mdss>;
1963 assigned-clocks = <&mmcc BYTE0_CLK_SRC>, <&mmcc PCLK0_CLK_SRC>;
1964 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
1973 clock-names = "mdp_core",
1985 #address-cells = <1>;
1986 #size-cells = <0>;
1989 #address-cells = <1>;
1990 #size-cells = <0>;
1995 remote-endpoint = <&mdp5_intf1_out>;
2008 compatible = "qcom,dsi-phy-28nm-hpm";
2012 reg-names = "dsi_pll",
2016 #clock-cells = <1>;
2017 #phy-cells = <0>;
2020 clock-names = "iface", "ref";
2025 mdss_dsi1: dsi@fd922e00 {
2026 compatible = "qcom,msm8974-dsi-ctrl",
2027 "qcom,mdss-dsi-ctrl";
2029 reg-names = "dsi_ctrl";
2031 interrupt-parent = <&mdss>;
2034 assigned-clocks = <&mmcc BYTE1_CLK_SRC>, <&mmcc PCLK1_CLK_SRC>;
2035 assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>;
2044 clock-names = "mdp_core",
2056 #address-cells = <1>;
2057 #size-cells = <0>;
2060 #address-cells = <1>;
2061 #size-cells = <0>;
2066 remote-endpoint = <&mdp5_intf2_out>;
2079 compatible = "qcom,dsi-phy-28nm-hpm";
2083 reg-names = "dsi_pll",
2087 #clock-cells = <1>;
2088 #phy-cells = <0>;
2091 clock-names = "iface", "ref";
2098 compatible = "qcom,msm8974-cci";
2099 #address-cells = <1>;
2100 #size-cells = <0>;
2106 clock-names = "camss_top_ahb",
2110 pinctrl-names = "default", "sleep";
2111 pinctrl-0 = <&cci_default>;
2112 pinctrl-1 = <&cci_sleep>;
2116 cci_i2c0: i2c-bus@0 {
2118 clock-frequency = <100000>;
2119 #address-cells = <1>;
2120 #size-cells = <0>;
2123 cci_i2c1: i2c-bus@1 {
2125 clock-frequency = <100000>;
2126 #address-cells = <1>;
2127 #size-cells = <0>;
2132 compatible = "qcom,adreno-330.1", "qcom,adreno";
2134 reg-names = "kgsl_3d0_reg_memory";
2137 interrupt-names = "kgsl_3d0_irq";
2142 clock-names = "core", "iface", "mem_iface";
2145 power-domains = <&mmcc OXILICX_GDSC>;
2146 operating-points-v2 = <&gpu_opp_table>;
2150 interconnect-names = "gfx-mem", "ocmem";
2156 gpu_opp_table: opp-table {
2157 compatible = "operating-points-v2";
2159 opp-320000000 {
2160 opp-hz = /bits/ 64 <320000000>;
2163 opp-200000000 {
2164 opp-hz = /bits/ 64 <200000000>;
2167 opp-27000000 {
2168 opp-hz = /bits/ 64 <27000000>;
2174 compatible = "qcom,msm8974-ocmem";
2177 reg-names = "ctrl", "mem";
2181 clock-names = "core", "iface";
2183 #address-cells = <1>;
2184 #size-cells = <1>;
2186 gmu_sram: gmu-sram@0 {
2192 compatible = "qcom,msm8974-adsp-pil";
2195 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
2200 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
2203 clock-names = "xo";
2205 memory-region = <&adsp_region>;
2207 qcom,smem-states = <&adsp_smp2p_out 0>;
2208 qcom,smem-state-names = "stop";
2212 smd-edge {
2216 qcom,smd-edge = <1>;
2222 compatible = "qcom,msm8974-imem", "syscon", "simple-mfd";
2225 reboot-mode {
2226 compatible = "syscon-reboot-mode";
2232 thermal-zones {
2233 cpu0-thermal {
2234 polling-delay-passive = <250>;
2235 polling-delay = <1000>;
2237 thermal-sensors = <&tsens 5>;
2253 cpu1-thermal {
2254 polling-delay-passive = <250>;
2255 polling-delay = <1000>;
2257 thermal-sensors = <&tsens 6>;
2273 cpu2-thermal {
2274 polling-delay-passive = <250>;
2275 polling-delay = <1000>;
2277 thermal-sensors = <&tsens 7>;
2293 cpu3-thermal {
2294 polling-delay-passive = <250>;
2295 polling-delay = <1000>;
2297 thermal-sensors = <&tsens 8>;
2313 q6-dsp-thermal {
2314 polling-delay-passive = <250>;
2315 polling-delay = <1000>;
2317 thermal-sensors = <&tsens 1>;
2320 q6_dsp_alert0: trip-point0 {
2328 modemtx-thermal {
2329 polling-delay-passive = <250>;
2330 polling-delay = <1000>;
2332 thermal-sensors = <&tsens 2>;
2335 modemtx_alert0: trip-point0 {
2343 video-thermal {
2344 polling-delay-passive = <250>;
2345 polling-delay = <1000>;
2347 thermal-sensors = <&tsens 3>;
2350 video_alert0: trip-point0 {
2358 wlan-thermal {
2359 polling-delay-passive = <250>;
2360 polling-delay = <1000>;
2362 thermal-sensors = <&tsens 4>;
2365 wlan_alert0: trip-point0 {
2373 gpu-top-thermal {
2374 polling-delay-passive = <250>;
2375 polling-delay = <1000>;
2377 thermal-sensors = <&tsens 9>;
2380 gpu1_alert0: trip-point0 {
2388 gpu-bottom-thermal {
2389 polling-delay-passive = <250>;
2390 polling-delay = <1000>;
2392 thermal-sensors = <&tsens 10>;
2395 gpu2_alert0: trip-point0 {
2405 compatible = "arm,armv7-timer";
2410 clock-frequency = <19200000>;