Lines Matching +full:0 +full:xfc4cb000
20 #clock-cells = <0>;
26 #clock-cells = <0>;
33 #size-cells = <0>;
34 interrupts = <GIC_PPI 9 0xf04>;
36 CPU0: cpu@0 {
40 reg = <0>;
108 reg = <0x0 0x0>;
113 interrupts = <GIC_PPI 7 0xf04>;
133 qcom,ipc = <&apcs 8 0>;
156 reg = <0x08000000 0x5100000>;
161 reg = <0x0d100000 0x100000>;
166 reg = <0x0d200000 0xa00000>;
171 reg = <0x0dc00000 0x1900000>;
176 reg = <0x0f500000 0x500000>;
181 reg = <0xfa00000 0x200000>;
186 reg = <0x0fc00000 0x160000>;
191 reg = <0x0fd60000 0x20000>;
197 reg = <0x0fd80000 0x180000>;
222 qcom,local-pid = <0>;
247 qcom,local-pid = <0>;
272 qcom,local-pid = <0>;
293 #size-cells = <0>;
299 apps_smsm: apps@0 {
300 reg = <0>;
340 reg = <0xf9000000 0x1000>,
341 <0xf9002000 0x1000>;
346 reg = <0xf9011000 0x1000>;
351 reg = <0xf9012000 0x1000>;
357 reg = <0xf9017000 0x1000>;
368 reg = <0xf9020000 0x1000>;
372 frame-number = <0>;
375 reg = <0xf9021000 0x1000>,
376 <0xf9022000 0x1000>;
382 reg = <0xf9023000 0x1000>;
389 reg = <0xf9024000 0x1000>;
396 reg = <0xf9025000 0x1000>;
403 reg = <0xf9026000 0x1000>;
410 reg = <0xf9027000 0x1000>;
417 reg = <0xf9028000 0x1000>;
424 reg = <0xf9088000 0x1000>, <0xf9008000 0x1000>;
429 reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>;
434 reg = <0xf9098000 0x1000>, <0xf9008000 0x1000>;
439 reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>;
444 reg = <0xf90a8000 0x1000>, <0xf9008000 0x1000>;
449 reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>;
454 reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>;
459 reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>;
464 reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
481 reg = <0xf9864900 0x11c>, <0xf9864000 0x800>;
493 #size-cells = <0>;
500 reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
512 #size-cells = <0>;
519 reg = <0xf991d000 0x1000>;
528 reg = <0xf991e000 0x1000>;
533 pinctrl-0 = <&blsp1_uart2_default>;
540 reg = <0xf9923000 0x1000>;
541 interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>;
545 pinctrl-0 = <&blsp1_i2c1_default>;
548 #size-cells = <0>;
554 reg = <0xf9924000 0x1000>;
559 pinctrl-0 = <&blsp1_i2c2_default>;
562 #size-cells = <0>;
568 reg = <0xf9925000 0x1000>;
569 interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>;
573 pinctrl-0 = <&blsp1_i2c3_default>;
576 #size-cells = <0>;
582 reg = <0xf9928000 0x1000>;
587 pinctrl-0 = <&blsp1_i2c6_default>;
590 #size-cells = <0>;
595 reg = <0xf9944000 0x19000>;
600 qcom,ee = <0>;
605 reg = <0xf995d000 0x1000>;
610 pinctrl-0 = <&blsp2_uart1_default>;
617 reg = <0xf995e000 0x1000>;
626 reg = <0xf9960000 0x1000>;
631 pinctrl-0 = <&blsp2_uart4_default>;
638 reg = <0xf9964000 0x1000>;
643 pinctrl-0 = <&blsp2_i2c2_default>;
646 #size-cells = <0>;
652 reg = <0xf9967000 0x1000>;
659 pinctrl-0 = <&blsp2_i2c5_default>;
662 #size-cells = <0>;
668 reg = <0xf9968000 0x1000>;
669 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
673 pinctrl-0 = <&blsp2_i2c6_default>;
676 #size-cells = <0>;
681 reg = <0xf9a55000 0x200>,
682 <0xf9a55200 0x200>;
693 ahb-burst-config = <0>;
699 usb_hs1_phy: phy-0 {
702 #phy-cells = <0>;
705 resets = <&gcc GCC_USB2A_PHY_BCR>, <&usb 0>;
713 #phy-cells = <0>;
725 reg = <0xf9bff000 0x200>;
732 reg = <0xfb204000 0x2000>, <0xfb202000 0x1000>, <0xfb21b000 0x3000>;
738 <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
744 qcom,smem-states = <&wcnss_smp2p_out 0>;
790 reg = <0xfc190000 0x10000>;
795 reg = <0xfc307000 0x1000>;
819 reg = <0xfc318000 0x1000>;
835 reg = <0xfc31a000 0x1000>;
842 #size-cells = <0>;
846 * 0 - not-connected
873 reg = <0xfc31b000 0x1000>;
880 #size-cells = <0>;
884 * 0 - connected trought funnel to Audio, Modem and
907 reg = <0xfc31c000 0x1000>;
914 #size-cells = <0>;
916 port@0 {
917 reg = <0>;
941 reg = <0xfc322000 0x1000>;
957 reg = <0xfc33c000 0x1000>;
975 reg = <0xfc33d000 0x1000>;
993 reg = <0xfc33e000 0x1000>;
1011 reg = <0xfc33f000 0x1000>;
1030 reg = <0xfc345000 0x1000>;
1037 #size-cells = <0>;
1039 port@0 {
1040 reg = <0>;
1075 reg = <0xfc380000 0x6a000>;
1088 reg = <0xfc400000 0x4000>;
1098 reg = <0xfc428000 0x4000>;
1102 ranges = <0 0xfc428000 0x4000>;
1105 reg = <0x150 0x14>;
1109 reg = <0xb50 0x14>;
1113 reg = <0x1550 0x14>;
1117 reg = <0x1f50 0x14>;
1122 reg = <0xfc460000 0x4000>;
1131 reg = <0xfc468000 0x4000>;
1140 reg = <0xfc470000 0x4000>;
1149 reg = <0xfc478000 0x4000>;
1158 reg = <0xfc480000 0x4000>;
1168 reg = <0xfc4a9000 0x1000>, /* TM */
1169 <0xfc4a8000 0x1000>; /* SROT */
1232 reg = <0xfc4ab000 0x4>;
1237 reg = <0xfc4bc000 0x1000>;
1242 reg = <0xd0 0x1>;
1243 bits = <0 8>;
1247 reg = <0xd1 0x1>;
1248 bits = <0 6>;
1252 reg = <0xd1 0x2>;
1257 reg = <0xd2 0x2>;
1262 reg = <0xd3 0x1>;
1267 reg = <0xd4 0x1>;
1268 bits = <0 6>;
1272 reg = <0xd4 0x2>;
1277 reg = <0xd5 0x2>;
1282 reg = <0xd6 0x1>;
1287 reg = <0xd7 0x1>;
1288 bits = <0 6>;
1292 reg = <0xd7 0x1>;
1297 reg = <0xd8 0x1>;
1298 bits = <0 6>;
1302 reg = <0xd8 0x2>;
1307 reg = <0xd9 0x2>;
1312 reg = <0xda 0x2>;
1317 reg = <0xdb 0x1>;
1322 reg = <0xdc 0x1>;
1323 bits = <0 6>;
1327 reg = <0xdc 0x2>;
1332 reg = <0xdd 0x2>;
1337 reg = <0xde 0x2>;
1342 reg = <0xdf 0x1>;
1343 bits = <0 6>;
1347 reg = <0xe0 0x1>;
1348 bits = <0 6>;
1352 reg = <0xe0 0x2>;
1357 reg = <0xe1 0x2>;
1362 reg = <0xe2 0x2>;
1367 reg = <0xe3 0x2>;
1368 bits = <0 6>;
1372 reg = <0xe3 0x1>;
1377 reg = <0xe4 0x1>;
1378 bits = <0 6>;
1382 reg = <0xe4 0x2>;
1387 reg = <0xe5 0x2>;
1392 reg = <0xe6 0x2>;
1397 reg = <0xe7 0x1>;
1398 bits = <0 6>;
1402 reg = <0x440 0x1>;
1403 bits = <0 8>;
1407 reg = <0x441 0x1>;
1408 bits = <0 6>;
1412 reg = <0x441 0x2>;
1417 reg = <0x442 0x2>;
1422 reg = <0x443 0x1>;
1427 reg = <0x444 0x1>;
1428 bits = <0 6>;
1432 reg = <0x444 0x2>;
1437 reg = <0x445 0x2>;
1442 reg = <0x446 0x1>;
1447 reg = <0x447 0x1>;
1452 reg = <0x448 0x1>;
1453 bits = <0 6>;
1457 reg = <0x448 0x2>;
1462 reg = <0x449 0x2>;
1467 reg = <0x44a 0x2>;
1472 reg = <0x44b 0x3>;
1477 reg = <0x44c 0x1>;
1478 bits = <0 6>;
1482 reg = <0x44c 0x2>;
1487 reg = <0x44d 0x2>;
1492 reg = <0x44e 0x1>;
1500 reg = <0xfc4cf000 0x1000>,
1501 <0xfc4cb000 0x1000>,
1502 <0xfc4ca000 0x1000>;
1505 qcom,ee = <0>;
1506 qcom,channel = <0>;
1508 #size-cells = <0>;
1515 reg = <0xfc834000 0x7000>;
1518 qcom,ee = <0>;
1527 reg = <0xfc880000 0x100>, <0xfc820000 0x020>;
1531 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1546 qcom,halt-regs = <&tcsr_mutex 0x1180 0x1200 0x1280>;
1548 qcom,smem-states = <&modem_smp2p_out 0>;
1579 qcom,smd-edge = <0>;
1587 reg = <0xfd484000 0x2000>;
1593 reg = <0xfd4a0000 0x10000>;
1598 reg = <0xfd510000 0x4000>;
1600 gpio-ranges = <&tlmm 0 0 146>;
1867 reg = <0xfd8c0000 0x6000>;
1874 <&mdss_dsi0_phy 0>,
1876 <&mdss_dsi1_phy 0>,
1877 <0>,
1878 <0>,
1879 <0>;
1896 reg = <0xfd900000 0x100>, <0xfd924000 0x1000>;
1919 reg = <0xfd900100 0x22000>;
1923 interrupts = <0>;
1936 #size-cells = <0>;
1938 port@0 {
1939 reg = <0>;
1957 reg = <0xfd922800 0x1f8>;
1964 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
1986 #size-cells = <0>;
1990 #size-cells = <0>;
1992 port@0 {
1993 reg = <0>;
2009 reg = <0xfd922a00 0xd4>,
2010 <0xfd922b00 0x280>,
2011 <0xfd922d80 0x30>;
2017 #phy-cells = <0>;
2028 reg = <0xfd922e00 0x1f8>;
2035 assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>;
2057 #size-cells = <0>;
2061 #size-cells = <0>;
2063 port@0 {
2064 reg = <0>;
2080 reg = <0xfd923000 0xd4>,
2081 <0xfd923100 0x280>,
2082 <0xfd923380 0x30>;
2088 #phy-cells = <0>;
2100 #size-cells = <0>;
2101 reg = <0xfda0c000 0x1000>;
2111 pinctrl-0 = <&cci_default>;
2116 cci_i2c0: i2c-bus@0 {
2117 reg = <0>;
2120 #size-cells = <0>;
2127 #size-cells = <0>;
2133 reg = <0xfdb00000 0x10000>;
2152 // iommus = <&gpu_iommu 0>;
2175 reg = <0xfdd00000 0x2000>,
2176 <0xfec00000 0x180000>;
2178 ranges = <0 0xfec00000 0x180000>;
2186 gmu_sram: gmu-sram@0 {
2187 reg = <0x0 0x100000>;
2193 reg = <0xfe200000 0x100>;
2196 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2207 qcom,smem-states = <&adsp_smp2p_out 0>;
2223 reg = <0xfe805000 0x1000>;
2227 offset = <0x65c>;
2406 interrupts = <GIC_PPI 2 0xf08>,
2407 <GIC_PPI 3 0xf08>,
2408 <GIC_PPI 4 0xf08>,
2409 <GIC_PPI 1 0xf08>;