Lines Matching +full:pm8921 +full:- +full:rtc
1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/clock/qcom,gcc-msm8960.h>
6 #include <dt-bindings/reset/qcom,gcc-msm8960.h>
7 #include <dt-bindings/clock/qcom,lcc-msm8960.h>
8 #include <dt-bindings/mfd/qcom-rpm.h>
9 #include <dt-bindings/soc/qcom,gsbi.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
16 interrupt-parent = <&intc>;
19 #address-cells = <1>;
20 #size-cells = <0>;
25 enable-method = "qcom,kpss-acc-v1";
28 next-level-cache = <&L2>;
35 enable-method = "qcom,kpss-acc-v1";
38 next-level-cache = <&L2>;
43 L2: l2-cache {
45 cache-level = <2>;
46 cache-unified;
55 cpu-pmu {
56 compatible = "qcom,krait-pmu";
58 qcom,no-pc-write;
63 compatible = "fixed-clock";
64 #clock-cells = <0>;
65 clock-frequency = <19200000>;
66 clock-output-names = "cxo_board";
70 compatible = "fixed-clock";
71 #clock-cells = <0>;
72 clock-frequency = <27000000>;
73 clock-output-names = "pxo_board";
77 compatible = "fixed-clock";
78 #clock-cells = <0>;
79 clock-frequency = <32768>;
80 clock-output-names = "sleep_clk";
85 vsdcc_fixed: vsdcc-regulator {
86 compatible = "regulator-fixed";
87 regulator-name = "SDCC Power";
88 regulator-min-microvolt = <2700000>;
89 regulator-max-microvolt = <2700000>;
90 regulator-always-on;
94 #address-cells = <1>;
95 #size-cells = <1>;
97 compatible = "simple-bus";
99 intc: interrupt-controller@2000000 {
100 compatible = "qcom,msm-qgic2";
101 interrupt-controller;
102 #interrupt-cells = <3>;
108 compatible = "qcom,kpss-wdt-msm8960", "qcom,kpss-timer",
109 "qcom,msm-timer";
114 clock-frequency = <27000000>;
115 cpu-offset = <0x80000>;
119 compatible = "qcom,msm8960-pinctrl";
120 gpio-controller;
121 gpio-ranges = <&msmgpio 0 0 152>;
122 #gpio-cells = <2>;
124 interrupt-controller;
125 #interrupt-cells = <2>;
129 gcc: clock-controller@900000 {
130 compatible = "qcom,gcc-msm8960";
131 #clock-cells = <1>;
132 #power-domain-cells = <1>;
133 #reset-cells = <1>;
138 clock-names = "cxo", "pxo", "pll4";
141 lcc: clock-controller@28000000 {
142 compatible = "qcom,lcc-msm8960";
144 #clock-cells = <1>;
145 #reset-cells = <1>;
152 clock-names = "pxo",
162 clock-controller@4000000 {
163 compatible = "qcom,mmcc-msm8960";
165 #clock-cells = <1>;
166 #power-domain-cells = <1>;
167 #reset-cells = <1>;
176 clock-names = "pxo",
186 l2cc: clock-controller@2011000 {
187 compatible = "qcom,kpss-gcc-msm8960", "qcom,kpss-gcc", "syscon";
190 clock-names = "pll8_vote", "pxo";
191 #clock-cells = <0>;
195 compatible = "qcom,rpm-msm8960";
202 interrupt-names = "ack", "err", "wakeup";
205 acc0: clock-controller@2088000 {
206 compatible = "qcom,kpss-acc-v1";
209 clock-names = "pll8_vote", "pxo";
210 clock-output-names = "acpu0_aux";
211 #clock-cells = <0>;
214 acc1: clock-controller@2098000 {
215 compatible = "qcom,kpss-acc-v1";
218 clock-names = "pll8_vote", "pxo";
219 clock-output-names = "acpu1_aux";
220 #clock-cells = <0>;
236 compatible = "qcom,gsbi-v1.0.0";
237 cell-index = <5>;
240 clock-names = "iface";
241 #address-cells = <1>;
242 #size-cells = <1>;
245 syscon-tcsr = <&tcsr>;
248 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
253 clock-names = "core", "iface";
261 qcom,controller-type = "pmic-arbiter";
268 clock-names = "core";
273 arm,primecell-periphid = <0x00051180>;
278 clock-names = "mclk", "apb_pclk";
279 bus-width = <4>;
280 cap-sd-highspeed;
281 cap-mmc-highspeed;
282 max-frequency = <192000000>;
283 no-1-8-v;
284 vmmc-supply = <&vsdcc_fixed>;
290 arm,primecell-periphid = <0x00051180>;
294 clock-names = "mclk", "apb_pclk";
295 bus-width = <8>;
296 max-frequency = <96000000>;
297 non-removable;
298 cap-sd-highspeed;
299 cap-mmc-highspeed;
300 vmmc-supply = <&vsdcc_fixed>;
304 compatible = "qcom,tcsr-msm8960", "syscon";
309 compatible = "qcom,gsbi-v1.0.0";
310 cell-index = <1>;
313 clock-names = "iface";
314 #address-cells = <1>;
315 #size-cells = <1>;
319 compatible = "qcom,spi-qup-v1.1.1";
320 #address-cells = <1>;
321 #size-cells = <0>;
324 cs-gpios = <&msmgpio 8 0>;
327 clock-names = "core", "iface";
333 compatible = "qcom,ci-hdrc";
338 clock-names = "core", "iface";
339 assigned-clocks = <&gcc USB_HS1_XCVR_CLK>;
340 assigned-clock-rates = <60000000>;
342 reset-names = "core";
344 ahb-burst-config = <0>;
346 phy-names = "usb-phy";
347 #reset-cells = <1>;
352 compatible = "qcom,usb-hs-phy-msm8960",
353 "qcom,usb-hs-phy";
355 clock-names = "sleep", "ref";
357 reset-names = "por";
358 #phy-cells = <0>;