Lines Matching +full:kpss +full:- +full:timer
1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/clock/qcom,gcc-msm8660.h>
7 #include <dt-bindings/soc/qcom,gsbi.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
14 interrupt-parent = <&intc>;
17 #address-cells = <1>;
18 #size-cells = <0>;
22 enable-method = "qcom,gcc-msm8660";
25 next-level-cache = <&L2>;
30 enable-method = "qcom,gcc-msm8660";
33 next-level-cache = <&L2>;
36 L2: l2-cache {
38 cache-level = <2>;
39 cache-unified;
48 cpu-pmu {
49 compatible = "qcom,scorpion-mp-pmu";
54 cxo_board: cxo-board-clk {
55 compatible = "fixed-clock";
56 #clock-cells = <0>;
57 clock-frequency = <19200000>;
58 clock-output-names = "cxo_board";
61 pxo_board: pxo-board-clk {
62 compatible = "fixed-clock";
63 #clock-cells = <0>;
64 clock-frequency = <27000000>;
65 clock-output-names = "pxo_board";
68 sleep-clk {
69 compatible = "fixed-clock";
70 #clock-cells = <0>;
71 clock-frequency = <32768>;
72 clock-output-names = "sleep_clk";
77 #address-cells = <1>;
78 #size-cells = <1>;
80 compatible = "simple-bus";
82 intc: interrupt-controller@2080000 {
83 compatible = "qcom,msm-8660-qgic";
84 interrupt-controller;
85 #interrupt-cells = <3>;
90 timer@2000000 {
91 compatible = "qcom,scss-timer", "qcom,msm-timer";
96 clock-frequency = <27000000>,
98 cpu-offset = <0x40000>;
102 compatible = "qcom,msm8660-pinctrl";
105 gpio-controller;
106 gpio-ranges = <&tlmm 0 0 173>;
107 #gpio-cells = <2>;
109 interrupt-controller;
110 #interrupt-cells = <2>;
114 gcc: clock-controller@900000 {
115 compatible = "qcom,gcc-msm8660";
116 #clock-cells = <1>;
117 #power-domain-cells = <1>;
118 #reset-cells = <1>;
121 clock-names = "pxo", "cxo";
125 compatible = "qcom,gsbi-v1.0.0";
126 cell-index = <12>;
129 clock-names = "iface";
130 #address-cells = <1>;
131 #size-cells = <1>;
134 syscon-tcsr = <&tcsr>;
139 compatible = "qcom,spi-qup-v1.1.1";
143 clock-names = "core", "iface";
144 #address-cells = <1>;
145 #size-cells = <0>;
151 compatible = "qcom,gsbi-v1.0.0";
152 cell-index = <12>;
155 clock-names = "iface";
156 #address-cells = <1>;
157 #size-cells = <1>;
160 syscon-tcsr = <&tcsr>;
164 compatible = "qcom,i2c-qup-v1.1.1";
168 clock-names = "core", "iface";
169 #address-cells = <1>;
170 #size-cells = <0>;
176 compatible = "qcom,gsbi-v1.0.0";
177 cell-index = <12>;
180 clock-names = "iface";
181 #address-cells = <1>;
182 #size-cells = <1>;
186 syscon-tcsr = <&tcsr>;
189 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
194 clock-names = "core", "iface";
199 compatible = "qcom,i2c-qup-v1.1.1";
203 clock-names = "core", "iface";
204 #address-cells = <1>;
205 #size-cells = <0>;
211 compatible = "qcom,gsbi-v1.0.0";
212 cell-index = <12>;
215 clock-names = "iface";
216 #address-cells = <1>;
217 #size-cells = <1>;
221 syscon-tcsr = <&tcsr>;
224 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
229 clock-names = "core", "iface";
234 compatible = "qcom,i2c-qup-v1.1.1";
238 clock-names = "core", "iface";
239 #address-cells = <1>;
240 #size-cells = <0>;
246 compatible = "qcom,gsbi-v1.0.0";
247 cell-index = <12>;
250 clock-names = "iface";
251 #address-cells = <1>;
252 #size-cells = <1>;
255 syscon-tcsr = <&tcsr>;
259 compatible = "qcom,i2c-qup-v1.1.1";
263 clock-names = "core", "iface";
264 #address-cells = <1>;
265 #size-cells = <0>;
271 compatible = "qcom,gsbi-v1.0.0";
272 cell-index = <12>;
275 clock-names = "iface";
276 #address-cells = <1>;
277 #size-cells = <1>;
280 syscon-tcsr = <&tcsr>;
283 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
288 clock-names = "core", "iface";
293 compatible = "qcom,i2c-qup-v1.1.1";
297 clock-names = "core", "iface";
298 #address-cells = <1>;
299 #size-cells = <0>;
304 ebi2: external-bus@1a100000 {
305 compatible = "qcom,msm8660-ebi2";
306 #address-cells = <2>;
307 #size-cells = <1>;
315 reg-names = "ebi2", "xmem";
317 clock-names = "ebi2x", "ebi2";
324 qcom,controller-type = "pmic-arbiter";
327 l2cc: clock-controller@2082000 {
328 compatible = "qcom,kpss-gcc-msm8660", "qcom,kpss-gcc", "syscon";
333 compatible = "qcom,rpm-msm8660";
340 interrupt-names = "ack", "err", "wakeup";
342 clock-names = "ram";
344 rpmcc: clock-controller {
345 compatible = "qcom,rpmcc-msm8660", "qcom,rpmcc";
346 #clock-cells = <1>;
348 clock-names = "pxo";
353 compatible = "simple-bus";
354 #address-cells = <1>;
355 #size-cells = <1>;
360 arm,primecell-periphid = <0x00051180>;
364 clock-names = "mclk", "apb_pclk";
365 bus-width = <8>;
366 max-frequency = <48000000>;
367 non-removable;
368 cap-sd-highspeed;
369 cap-mmc-highspeed;
375 arm,primecell-periphid = <0x00051180>;
379 clock-names = "mclk", "apb_pclk";
380 bus-width = <8>;
381 max-frequency = <48000000>;
382 cap-sd-highspeed;
383 cap-mmc-highspeed;
388 arm,primecell-periphid = <0x00051180>;
393 clock-names = "mclk", "apb_pclk";
394 bus-width = <4>;
395 cap-sd-highspeed;
396 cap-mmc-highspeed;
397 max-frequency = <48000000>;
398 no-1-8-v;
403 arm,primecell-periphid = <0x00051180>;
408 clock-names = "mclk", "apb_pclk";
409 bus-width = <4>;
410 max-frequency = <48000000>;
411 cap-sd-highspeed;
412 cap-mmc-highspeed;
417 arm,primecell-periphid = <0x00051180>;
422 clock-names = "mclk", "apb_pclk";
423 bus-width = <4>;
424 cap-sd-highspeed;
425 cap-mmc-highspeed;
426 max-frequency = <48000000>;
431 compatible = "qcom,tcsr-msm8660", "syscon";