Lines Matching +full:0 +full:x1b000000

18 		#size-cells = <0>;
20 		cpu@0 {
24 			reg = <0>;
45 		reg = <0x0 0x0>;
50 		interrupts = <1 9 0x304>;
56 			#clock-cells = <0>;
63 			#clock-cells = <0>;
70 			#clock-cells = <0>;
86 			reg = < 0x02080000 0x1000 >,
87 			      < 0x02081000 0x1000 >;
92 			interrupts = <1 0 0x301>,
93 				     <1 1 0x301>,
94 				     <1 2 0x301>;
95 			reg = <0x02000000 0x100>;
98 			cpu-offset = <0x40000>;
103 			reg = <0x800000 0x4000>;
106 			gpio-ranges = <&tlmm 0 0 173>;
108 			interrupts = <0 16 0x4>;
119 			reg = <0x900000 0x4000>;
127 			reg = <0x16000000 0x100>;
140 				reg = <0x16080000 0x1000>;
145 				#size-cells = <0>;
153 			reg = <0x16200000 0x100>;
165 				reg = <0x16280000 0x1000>;
170 				#size-cells = <0>;
178 			reg = <0x16500000 0x100>;
190 				reg = <0x16540000 0x1000>,
191 				      <0x16500000 0x1000>;
200 				reg = <0x16580000 0x1000>;
205 				#size-cells = <0>;
213 			reg = <0x16600000 0x100>;
225 				reg = <0x16640000 0x1000>,
226 				      <0x16600000 0x1000>;
235 				reg = <0x16680000 0x1000>;
240 				#size-cells = <0>;
248 			reg = <0x19800000 0x100>;
260 				reg = <0x19880000 0x1000>;
265 				#size-cells = <0>;
273 			reg = <0x19c00000 0x100>;
284 				reg = <0x19c40000 0x1000>,
285 				      <0x19c00000 0x1000>;
286 				interrupts = <0 195 IRQ_TYPE_LEVEL_HIGH>;
294 				reg = <0x19c80000 0x1000>;
295 				interrupts = <0 196 IRQ_TYPE_LEVEL_HIGH>;
299 				#size-cells = <0>;
308 			ranges = <0 0x0 0x1a800000 0x00800000>,
309 				 <1 0x0 0x1b000000 0x00800000>,
310 				 <2 0x0 0x1b800000 0x00800000>,
311 				 <3 0x0 0x1d000000 0x08000000>,
312 				 <4 0x0 0x1c800000 0x00800000>,
313 				 <5 0x0 0x1c000000 0x00800000>;
314 			reg = <0x1a100000 0x1000>, <0x1a110000 0x1000>;
323 			reg = <0x500000 0x1000>;
329 			reg = <0x02082000 0x1000>;
334 			reg = <0x00104000 0x1000>;
335 			qcom,ipc = <&l2cc 0x8 2>;
360 				arm,primecell-periphid = <0x00051180>;
361 				reg = <0x12400000 0x8000>;
375 				arm,primecell-periphid = <0x00051180>;
376 				reg = <0x12140000 0x8000>;
388 				arm,primecell-periphid = <0x00051180>;
390 				reg = <0x12180000 0x8000>;
403 				arm,primecell-periphid = <0x00051180>;
405 				reg = <0x121c0000 0x8000>;
417 				arm,primecell-periphid = <0x00051180>;
419 				reg = <0x12200000 0x8000>;
432 			reg = <0x1a400000 0x100>;