Lines Matching +full:0 +full:x3000000
23 memory@0 {
25 reg = <0x0 0x0>;
31 #clock-cells = <0>;
37 #clock-cells = <0>;
73 qcom,ipc = <&apcs 8 0>;
125 reg = <0x3000000 0x100000>;
130 reg = <0x0dc00000 0x1900000>;
153 qcom,local-pid = <0>;
177 reg = <0xf9000000 0x1000>,
178 <0xf9002000 0x1000>;
185 reg = <0xf9011000 0x1000>;
190 reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
200 pinctrl-0 = <&sdhc1_default_state>;
206 reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
216 pinctrl-0 = <&sdhc2_default_state>;
222 reg = <0xf9864900 0x11c>, <0xf9864000 0x800>;
232 pinctrl-0 = <&sdhc3_default_state>;
238 reg = <0xf991d000 0x1000>;
247 reg = <0xf991e000 0x1000>;
258 reg = <0xf991f000 0x1000>;
267 reg = <0xf9920000 0x1000>;
277 reg = <0xf9923000 0x1000>;
282 pinctrl-0 = <&blsp1_i2c1_pins>;
284 #size-cells = <0>;
290 reg = <0xf9924000 0x1000>;
295 pinctrl-0 = <&blsp1_i2c2_pins>;
297 #size-cells = <0>;
303 reg = <0xf9925000 0x1000>;
308 pinctrl-0 = <&blsp1_i2c3_pins>;
310 #size-cells = <0>;
316 reg = <0xf9926000 0x1000>;
321 pinctrl-0 = <&blsp1_i2c4_pins>;
323 #size-cells = <0>;
329 reg = <0xf9927000 0x1000>;
334 pinctrl-0 = <&blsp1_i2c5_pins>;
336 #size-cells = <0>;
341 reg = <0xf9928000 0x1000>;
347 pinctrl-0 = <&blsp1_i2c6_pins>;
350 #size-cells = <0>;
357 #size-cells = <0>;
358 reg = <0xfda0c000 0x1000>;
368 pinctrl-0 = <&cci_default>;
373 cci_i2c0: i2c-bus@0 {
374 reg = <0>;
377 #size-cells = <0>;
383 reg = <0xf9a55000 0x200>,
384 <0xf9a55200 0x200>;
398 ahb-burst-config = <0>;
408 #phy-cells = <0>;
412 resets = <&gcc GCC_USB2A_PHY_BCR>, <&usb 0>;
414 qcom,init-seq = /bits/ 8 <0x0 0x44
415 0x1 0x68 0x2 0x24 0x3 0x13>;
422 reg = <0xfc400000 0x4000>;
435 reg = <0xfd8c0000 0x6000>;
446 <&mdss_dsi0_phy 0>;
458 reg = <0xfd510000 0x4000>;
461 gpio-ranges = <&tlmm 0 0 117>;
578 reg = <0xfc4a9000 0x1000>, /* TM */
579 <0xfc4a8000 0x1000>; /* SROT */
606 reg = <0xfc4ab000 0x4>;
611 reg = <0xfc4bc000 0x1000>;
616 reg = <0x1c1 0x2>;
621 reg = <0x1c2 0x2>;
626 reg = <0x1c4 0x1>;
627 bits = <0 6>;
631 reg = <0x1c4 0x2>;
636 reg = <0x1c5 0x2>;
641 reg = <0x1c6 0x1>;
646 reg = <0x1c7 0x1>;
647 bits = <0 6>;
651 reg = <0x1ca 0x2>;
656 reg = <0x1cc 0x1>;
657 bits = <0 8>;
661 reg = <0x1cd 0x1>;
662 bits = <0 6>;
666 reg = <0x1cd 0x2>;
671 reg = <0x1ce 0x2>;
676 reg = <0x1cf 0x1>;
681 reg = <0x446 0x2>;
686 reg = <0x447 0x1>;
691 reg = <0x44e 0x1>;
696 reg = <0x44f 0x1>;
704 reg = <0xfc4cf000 0x1000>,
705 <0xfc4cb000 0x1000>,
706 <0xfc4ca000 0x1000>;
709 qcom,ee = <0>;
710 qcom,channel = <0>;
712 #size-cells = <0>;
719 reg = <0xf9bff000 0x200>;
726 reg = <0xf9020000 0x1000>;
732 frame-number = <0>;
735 reg = <0xf9021000 0x1000>,
736 <0xf9022000 0x1000>;
742 reg = <0xf9023000 0x1000>;
749 reg = <0xf9024000 0x1000>;
756 reg = <0xf9025000 0x1000>;
763 reg = <0xf9026000 0x1000>;
770 reg = <0xf9027000 0x1000>;
777 reg = <0xf9028000 0x1000>;
784 reg = <0xfc190000 0x10000>;
789 reg = <0xfc428000 0x4000>;
793 ranges = <0 0xfc428000 0x4000>;
796 reg = <0x150 0x14>;
800 reg = <0xb50 0x14>;
804 reg = <0x1550 0x14>;
808 reg = <0x1f50 0x14>;
814 reg = <0xfd484000 0x1000>;
820 reg = <0xfe200000 0x100>;
823 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
837 qcom,smem-states = <&adsp_smp2p_out 0>;
854 reg = <0xfdd00000 0x2000>,
855 <0xfec00000 0x20000>;
857 ranges = <0 0xfec00000 0x20000>;
864 gmu_sram: gmu-sram@0 {
865 reg = <0x0 0x20000>;
871 reg = <0xfe805000 0x1000>;
875 offset = <0x65c>;
877 mode-bootloader = <0x77665500>;
878 mode-normal = <0x77665501>;
879 mode-recovery = <0x77665502>;
885 reg = <0xfd900000 0x100>, <0xfd924000 0x1000>;
910 reg = <0xfd900100 0x22000>;
914 interrupts = <0>;
927 #size-cells = <0>;
929 port@0 {
930 reg = <0>;
941 reg = <0xfd922800 0x1f8>;
949 assigned-clock-parents = <&mdss_dsi0_phy 0>,
970 #size-cells = <0>;
974 #size-cells = <0>;
976 port@0 {
977 reg = <0>;
993 reg = <0xfd922a00 0xd4>,
994 <0xfd922b00 0x280>,
995 <0xfd922d80 0x30>;
1001 #phy-cells = <0>;
1012 reg = <0xfdb00000 0x10000>;