Lines Matching +full:pcie2 +full:- +full:phy
1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/mfd/qcom-rpm.h>
6 #include <dt-bindings/clock/qcom,rpmcc.h>
7 #include <dt-bindings/clock/qcom,gcc-ipq806x.h>
8 #include <dt-bindings/clock/qcom,lcc-ipq806x.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/reset/qcom,gcc-ipq806x.h>
11 #include <dt-bindings/soc/qcom,gsbi.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 #address-cells = <1>;
16 #size-cells = <1>;
19 interrupt-parent = <&intc>;
22 #address-cells = <1>;
23 #size-cells = <0>;
27 enable-method = "qcom,kpss-acc-v1";
30 next-level-cache = <&L2>;
37 enable-method = "qcom,kpss-acc-v1";
40 next-level-cache = <&L2>;
45 L2: l2-cache {
47 cache-level = <2>;
48 cache-unified;
52 thermal-zones {
53 sensor0-thermal {
54 polling-delay-passive = <0>;
55 polling-delay = <0>;
56 thermal-sensors = <&tsens 0>;
59 cpu-critical {
65 cpu-hot {
73 sensor1-thermal {
74 polling-delay-passive = <0>;
75 polling-delay = <0>;
76 thermal-sensors = <&tsens 1>;
79 cpu-critical {
85 cpu-hot {
93 sensor2-thermal {
94 polling-delay-passive = <0>;
95 polling-delay = <0>;
96 thermal-sensors = <&tsens 2>;
99 cpu-critical {
105 cpu-hot {
113 sensor3-thermal {
114 polling-delay-passive = <0>;
115 polling-delay = <0>;
116 thermal-sensors = <&tsens 3>;
119 cpu-critical {
125 cpu-hot {
133 sensor4-thermal {
134 polling-delay-passive = <0>;
135 polling-delay = <0>;
136 thermal-sensors = <&tsens 4>;
139 cpu-critical {
145 cpu-hot {
153 sensor5-thermal {
154 polling-delay-passive = <0>;
155 polling-delay = <0>;
156 thermal-sensors = <&tsens 5>;
159 cpu-critical {
165 cpu-hot {
173 sensor6-thermal {
174 polling-delay-passive = <0>;
175 polling-delay = <0>;
176 thermal-sensors = <&tsens 6>;
179 cpu-critical {
185 cpu-hot {
193 sensor7-thermal {
194 polling-delay-passive = <0>;
195 polling-delay = <0>;
196 thermal-sensors = <&tsens 7>;
199 cpu-critical {
205 cpu-hot {
213 sensor8-thermal {
214 polling-delay-passive = <0>;
215 polling-delay = <0>;
216 thermal-sensors = <&tsens 8>;
219 cpu-critical {
225 cpu-hot {
233 sensor9-thermal {
234 polling-delay-passive = <0>;
235 polling-delay = <0>;
236 thermal-sensors = <&tsens 9>;
239 cpu-critical {
245 cpu-hot {
253 sensor10-thermal {
254 polling-delay-passive = <0>;
255 polling-delay = <0>;
256 thermal-sensors = <&tsens 10>;
259 cpu-critical {
265 cpu-hot {
279 cpu-pmu {
280 compatible = "qcom,krait-pmu";
285 reserved-memory {
286 #address-cells = <1>;
287 #size-cells = <1>;
292 no-map;
298 no-map;
306 compatible = "fixed-clock";
307 #clock-cells = <0>;
308 clock-frequency = <25000000>;
312 compatible = "fixed-clock";
313 #clock-cells = <0>;
314 clock-frequency = <25000000>;
318 compatible = "fixed-clock";
319 clock-frequency = <32768>;
320 #clock-cells = <0>;
326 compatible = "qcom,scm-ipq806x", "qcom,scm";
330 stmmac_axi_setup: stmmac-axi-config {
336 vsdcc_fixed: vsdcc-regulator {
337 compatible = "regulator-fixed";
338 regulator-name = "SDCC Power";
339 regulator-min-microvolt = <3300000>;
340 regulator-max-microvolt = <3300000>;
341 regulator-always-on;
345 #address-cells = <1>;
346 #size-cells = <1>;
348 compatible = "simple-bus";
351 compatible = "qcom,rpm-ipq8064";
358 interrupt-names = "ack", "err", "wakeup";
361 clock-names = "ram";
363 rpmcc: clock-controller {
364 compatible = "qcom,rpmcc-ipq806x", "qcom,rpmcc";
365 #clock-cells = <1>;
372 qcom,controller-type = "pmic-arbiter";
376 compatible = "qcom,ipq8064-qfprom", "qcom,qfprom";
378 #address-cells = <1>;
379 #size-cells = <1>;
392 compatible = "qcom,ipq8064-pinctrl";
395 gpio-controller;
396 gpio-ranges = <&qcom_pinmux 0 0 69>;
397 #gpio-cells = <2>;
398 interrupt-controller;
399 #interrupt-cells = <2>;
406 drive-strength = <12>;
407 bias-disable;
415 drive-strength = <12>;
416 bias-disable;
424 drive-strength = <12>;
425 bias-disable;
429 i2c4_pins: i2c4-default {
432 drive-strength = <12>;
433 bias-disable;
440 drive-strength = <10>;
441 bias-none;
450 drive-strength = <2>;
451 bias-pull-down;
452 output-low;
459 drive-strength = <2>;
460 bias-pull-up;
472 drive-strength = <10>;
473 bias-disable;
479 drive-strength = <10>;
480 bias-pull-up;
488 drive-strength = <10>;
489 bias-bus-hold;
493 mdio0_pins: mdio0-pins {
497 drive-strength = <8>;
498 bias-disable;
502 rgmii2_pins: rgmii2-pins {
509 drive-strength = <8>;
510 bias-disable;
515 gcc: clock-controller@900000 {
516 compatible = "qcom,gcc-ipq8064", "syscon";
518 clock-names = "pxo", "cxo", "pll4";
520 #clock-cells = <1>;
521 #reset-cells = <1>;
522 #power-domain-cells = <1>;
524 tsens: thermal-sensor {
525 compatible = "qcom,ipq8064-tsens";
527 nvmem-cells = <&tsens_calib>, <&tsens_calib_backup>;
528 nvmem-cell-names = "calib", "calib_backup";
530 interrupt-names = "uplow";
533 #thermal-sensor-cells = <1>;
538 compatible = "qcom,sfpb-mutex";
541 #hwlock-cells = <1>;
544 intc: interrupt-controller@2000000 {
545 compatible = "qcom,msm-qgic2";
546 interrupt-controller;
547 #interrupt-cells = <3>;
553 compatible = "qcom,kpss-wdt-ipq8064", "qcom,kpss-timer",
554 "qcom,msm-timer";
566 clock-frequency = <25000000>;
568 clock-names = "sleep";
569 cpu-offset = <0x80000>;
572 l2cc: clock-controller@2011000 {
573 compatible = "qcom,kpss-gcc-ipq8064", "qcom,kpss-gcc", "syscon";
576 clock-names = "pll8_vote", "pxo";
577 #clock-cells = <0>;
580 acc0: clock-controller@2088000 {
581 compatible = "qcom,kpss-acc-v1";
584 clock-names = "pll8_vote", "pxo";
585 clock-output-names = "acpu0_aux";
586 #clock-cells = <0>;
595 acc1: clock-controller@2098000 {
596 compatible = "qcom,kpss-acc-v1";
599 clock-names = "pll8_vote", "pxo";
600 clock-output-names = "acpu1_aux";
601 #clock-cells = <0>;
616 compatible = "qcom,ipq8064-dwc3", "qcom,dwc3";
617 #address-cells = <1>;
618 #size-cells = <1>;
621 clock-names = "core";
626 reset-names = "master";
635 phy-names = "usb2-phy", "usb3-phy";
641 hs_phy_0: phy@100f8800 {
642 compatible = "qcom,ipq806x-usb-phy-hs";
645 clock-names = "ref";
646 #phy-cells = <0>;
651 ss_phy_0: phy@100f8830 {
652 compatible = "qcom,ipq806x-usb-phy-ss";
655 clock-names = "ref";
656 #phy-cells = <0>;
662 compatible = "qcom,ipq8064-dwc3", "qcom,dwc3";
663 #address-cells = <1>;
664 #size-cells = <1>;
667 clock-names = "core";
672 reset-names = "master";
681 phy-names = "usb2-phy", "usb3-phy";
687 hs_phy_1: phy@110f8800 {
688 compatible = "qcom,ipq806x-usb-phy-hs";
691 clock-names = "ref";
692 #phy-cells = <0>;
697 ss_phy_1: phy@110f8830 {
698 compatible = "qcom,ipq806x-usb-phy-ss";
701 clock-names = "ref";
702 #phy-cells = <0>;
707 sdcc3bam: dma-controller@12182000 {
708 compatible = "qcom,bam-v1.3.0";
712 clock-names = "bam_clk";
713 #dma-cells = <1>;
717 sdcc1bam: dma-controller@12402000 {
718 compatible = "qcom,bam-v1.3.0";
722 clock-names = "bam_clk";
723 #dma-cells = <1>;
728 compatible = "simple-bus";
729 #address-cells = <1>;
730 #size-cells = <1>;
735 arm,primecell-periphid = <0x00051180>;
740 clock-names = "mclk", "apb_pclk";
741 bus-width = <8>;
742 cap-sd-highspeed;
743 cap-mmc-highspeed;
744 max-frequency = <192000000>;
745 sd-uhs-sdr104;
746 sd-uhs-ddr50;
747 vqmmc-supply = <&vsdcc_fixed>;
749 dma-names = "tx", "rx";
755 arm,primecell-periphid = <0x00051180>;
759 clock-names = "mclk", "apb_pclk";
760 bus-width = <8>;
761 max-frequency = <96000000>;
762 non-removable;
763 cap-sd-highspeed;
764 cap-mmc-highspeed;
765 vmmc-supply = <&vsdcc_fixed>;
767 dma-names = "tx", "rx";
772 compatible = "qcom,gsbi-v1.0.0";
774 cell-index = <1>;
776 clock-names = "iface";
777 #address-cells = <1>;
778 #size-cells = <1>;
781 syscon-tcsr = <&tcsr>;
786 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
791 clock-names = "core", "iface";
797 compatible = "qcom,i2c-qup-v1.1.1";
801 clock-names = "core", "iface";
802 #address-cells = <1>;
803 #size-cells = <0>;
810 compatible = "qcom,gsbi-v1.0.0";
811 cell-index = <2>;
814 clock-names = "iface";
815 #address-cells = <1>;
816 #size-cells = <1>;
820 syscon-tcsr = <&tcsr>;
823 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
828 clock-names = "core", "iface";
833 compatible = "qcom,i2c-qup-v1.1.1";
838 clock-names = "core", "iface";
841 #address-cells = <1>;
842 #size-cells = <0>;
847 compatible = "qcom,gsbi-v1.0.0";
848 cell-index = <4>;
851 clock-names = "iface";
852 #address-cells = <1>;
853 #size-cells = <1>;
857 syscon-tcsr = <&tcsr>;
860 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
865 clock-names = "core", "iface";
870 compatible = "qcom,i2c-qup-v1.1.1";
875 clock-names = "core", "iface";
878 #address-cells = <1>;
879 #size-cells = <0>;
884 compatible = "qcom,gsbi-v1.0.0";
886 cell-index = <6>;
888 clock-names = "iface";
889 #address-cells = <1>;
890 #size-cells = <1>;
893 syscon-tcsr = <&tcsr>;
898 compatible = "qcom,i2c-qup-v1.1.1";
903 clock-names = "core", "iface";
905 #address-cells = <1>;
906 #size-cells = <0>;
912 compatible = "qcom,spi-qup-v1.1.1";
917 clock-names = "core", "iface";
919 #address-cells = <1>;
920 #size-cells = <0>;
928 compatible = "qcom,gsbi-v1.0.0";
929 cell-index = <7>;
932 clock-names = "iface";
933 #address-cells = <1>;
934 #size-cells = <1>;
936 syscon-tcsr = <&tcsr>;
939 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
944 clock-names = "core", "iface";
949 compatible = "qcom,i2c-qup-v1.1.1";
954 clock-names = "core", "iface";
956 #address-cells = <1>;
957 #size-cells = <0>;
963 adm_dma: dma-controller@18300000 {
967 #dma-cells = <1>;
970 clock-names = "core", "iface";
977 reset-names = "clk", "pbus", "c0", "c1", "c2";
984 compatible = "qcom,gsbi-v1.0.0";
985 cell-index = <5>;
988 clock-names = "iface";
989 #address-cells = <1>;
991 #size-cells = <1>;
995 syscon-tcsr = <&tcsr>;
998 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
1003 clock-names = "core", "iface";
1008 compatible = "qcom,i2c-qup-v1.1.1";
1013 clock-names = "core", "iface";
1016 #address-cells = <1>;
1017 #size-cells = <0>;
1021 compatible = "qcom,spi-qup-v1.1.1";
1026 clock-names = "core", "iface";
1029 #address-cells = <1>;
1030 #size-cells = <0>;
1035 compatible = "qcom,tcsr-ipq8064", "syscon";
1043 clock-names = "core";
1046 nand: nand-controller@1ac00000 {
1047 compatible = "qcom,ipq806x-nand";
1050 pinctrl-0 = <&nand_pins>;
1051 pinctrl-names = "default";
1055 clock-names = "core", "aon";
1058 dma-names = "rxtx";
1059 qcom,cmd-crci = <15>;
1060 qcom,data-crci = <3>;
1062 #address-cells = <1>;
1063 #size-cells = <0>;
1068 sata_phy: sata-phy@1b400000 {
1069 compatible = "qcom,ipq806x-sata-phy";
1073 clock-names = "cfg";
1075 #phy-cells = <0>;
1080 compatible = "qcom,pcie-ipq8064";
1085 reg-names = "dbi", "elbi", "parf", "config";
1087 linux,pci-domain = <0>;
1088 bus-range = <0x00 0xff>;
1089 num-lanes = <1>;
1090 #address-cells = <3>;
1091 #size-cells = <2>;
1097 interrupt-names = "msi";
1098 #interrupt-cells = <1>;
1099 interrupt-map-mask = <0 0 0 0x7>;
1100 interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1110 clock-names = "core", "iface", "phy", "aux", "ref";
1112 assigned-clocks = <&gcc PCIE_ALT_REF_CLK>;
1113 assigned-clock-rates = <100000000>;
1121 reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
1123 pinctrl-0 = <&pcie0_pins>;
1124 pinctrl-names = "default";
1127 perst-gpios = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>;
1131 compatible = "qcom,pcie-ipq8064";
1136 reg-names = "dbi", "elbi", "parf", "config";
1138 linux,pci-domain = <1>;
1139 bus-range = <0x00 0xff>;
1140 num-lanes = <1>;
1141 #address-cells = <3>;
1142 #size-cells = <2>;
1148 interrupt-names = "msi";
1149 #interrupt-cells = <1>;
1150 interrupt-map-mask = <0 0 0 0x7>;
1151 interrupt-map = <0 0 0 1 &intc 0 58 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1161 clock-names = "core", "iface", "phy", "aux", "ref";
1163 assigned-clocks = <&gcc PCIE_1_ALT_REF_CLK>;
1164 assigned-clock-rates = <100000000>;
1172 reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
1174 pinctrl-0 = <&pcie1_pins>;
1175 pinctrl-names = "default";
1178 perst-gpios = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>;
1181 pcie2: pcie@1b900000 {
1182 compatible = "qcom,pcie-ipq8064";
1187 reg-names = "dbi", "elbi", "parf", "config";
1189 linux,pci-domain = <2>;
1190 bus-range = <0x00 0xff>;
1191 num-lanes = <1>;
1192 #address-cells = <3>;
1193 #size-cells = <2>;
1199 interrupt-names = "msi";
1200 #interrupt-cells = <1>;
1201 interrupt-map-mask = <0 0 0 0x7>;
1202 interrupt-map = <0 0 0 1 &intc 0 72 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1212 clock-names = "core", "iface", "phy", "aux", "ref";
1214 assigned-clocks = <&gcc PCIE_2_ALT_REF_CLK>;
1215 assigned-clock-rates = <100000000>;
1223 reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
1225 pinctrl-0 = <&pcie2_pins>;
1226 pinctrl-names = "default";
1229 perst-gpios = <&qcom_pinmux 63 GPIO_ACTIVE_LOW>;
1237 lcc: clock-controller@28000000 {
1238 compatible = "qcom,lcc-ipq8064";
1240 #clock-cells = <1>;
1241 #reset-cells = <1>;
1245 compatible = "qcom,lpass-cpu";
1250 clock-names = "ahbix-clk",
1251 "mi2s-osr-clk",
1252 "mi2s-bit-clk";
1254 interrupt-names = "lpass-irq-lpaif";
1256 reg-names = "lpass-lpaif";
1260 compatible = "qcom,ipq806x-ahci", "generic-ahci";
1270 clock-names = "slave_face", "iface", "core",
1273 assigned-clocks = <&gcc SATA_RXOOB_CLK>, <&gcc SATA_PMALIVE_CLK>;
1274 assigned-clock-rates = <100000000>, <100000000>;
1277 phy-names = "sata-phy";
1283 compatible = "qcom,ipq806x-gmac", "snps,dwmac";
1286 interrupt-names = "macirq";
1288 snps,axi-config = <&stmmac_axi_setup>;
1292 qcom,nss-common = <&nss_common>;
1293 qcom,qsgmii-csr = <&qsgmii_csr>;
1296 clock-names = "stmmaceth";
1300 reset-names = "stmmaceth", "ahb";
1307 compatible = "qcom,ipq806x-gmac", "snps,dwmac";
1310 interrupt-names = "macirq";
1312 snps,axi-config = <&stmmac_axi_setup>;
1316 qcom,nss-common = <&nss_common>;
1317 qcom,qsgmii-csr = <&qsgmii_csr>;
1320 clock-names = "stmmaceth";
1324 reset-names = "stmmaceth", "ahb";
1331 compatible = "qcom,ipq806x-gmac", "snps,dwmac";
1334 interrupt-names = "macirq";
1336 snps,axi-config = <&stmmac_axi_setup>;
1340 qcom,nss-common = <&nss_common>;
1341 qcom,qsgmii-csr = <&qsgmii_csr>;
1344 clock-names = "stmmaceth";
1348 reset-names = "stmmaceth", "ahb";
1355 compatible = "qcom,ipq806x-gmac", "snps,dwmac";
1358 interrupt-names = "macirq";
1360 snps,axi-config = <&stmmac_axi_setup>;
1364 qcom,nss-common = <&nss_common>;
1365 qcom,qsgmii-csr = <&qsgmii_csr>;
1368 clock-names = "stmmaceth";
1372 reset-names = "stmmaceth", "ahb";